Vojta Mrazek
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1c2efef024
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automated verilog testing
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2022-02-02 13:19:54 +01:00 |
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Vojta Mrazek
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8c0f24cd2d
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General MAC circuit
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2021-09-06 12:52:13 +02:00 |
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Vojta Mrazek
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c6e542231c
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CGP tests; reversed output order
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2021-06-23 13:43:58 +02:00 |
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Vojta Mrazek
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cfe0ca6b4b
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Automated testing, preparing the package for publishing (#1)
* automated pandoc deploy
* automated pandoc deploy (v2)
* automated pandoc deploy (v2)
* automated pdoc deploy (v3)
* automated pdoc deploy (v4)
* automated pdoc deploy (v5)
* automated pdoc deploy (v5)
* prepare for python project
* 8-bit testing
* 8-bit testing
* 8-bit testing (v2)
* 8-bit testing (v3)
* update of sign
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2021-06-18 12:38:11 +02:00 |
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honzastor
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e5f2dd893a
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Fixed proper generated circuits names (mistakenly named cska as csa).
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2021-04-28 21:39:58 +02:00 |
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honzastor
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7a6d5213f8
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Updating gitignore
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2021-03-30 16:15:54 +02:00 |
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honzastor
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ef5dc80382
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Implemented generation to flat Verilog format and improved some other minor bits of code.
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2021-02-16 10:41:29 +01:00 |
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honzastor
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f1142b51d9
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Implemented basic tests for generated flat C code circuits.
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2021-02-09 21:02:50 +01:00 |
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honzastor
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4f8de30911
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Implementation organized into multiple scripts. Added basic generation example call. Adjusting code to PEP8 standard (except long lines).)
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2021-01-18 19:29:31 +01:00 |
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root
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7fba0f0aea
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Added ripple carry adder and started work on C code generation.
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2020-12-10 22:37:10 +01:00 |
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root
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99d23be531
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Implemented logic for wire, bus, logic gates, and 1-bit adders.
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2020-12-10 03:52:00 +01:00 |
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root
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a3ba1fca58
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Implemented logic for basic components such as logic gates, bus and wire. From these components were built primary low level 1-bit circuits (half, full adder).
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2020-12-10 03:45:46 +01:00 |
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