5 Commits

Author	SHA1	Message	Date
honzastor	ef5dc80382	Implemented generation to flat Verilog format and improved some other minor bits of code.	2021-02-16 10:41:29 +01:00
honzastor	f1142b51d9	Implemented basic tests for generated flat C code circuits.	2021-02-09 21:02:50 +01:00
honzastor	4f8de30911	Implementation organized into multiple scripts. Added basic generation example call. Adjusting code to PEP8 standard (except long lines).)	2021-01-18 19:29:31 +01:00
root	7fba0f0aea	Added ripple carry adder and started work on C code generation.	2020-12-10 22:37:10 +01:00
root	99d23be531	Implemented logic for wire, bus, logic gates, and 1-bit adders.	2020-12-10 03:52:00 +01:00