honzastor
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0d98fc0a2f
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Adding generated program documentation and chr2c.py script.
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2021-05-05 18:27:47 +02:00 |
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honzastor
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e5f2dd893a
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Fixed proper generated circuits names (mistakenly named cska as csa).
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2021-04-28 21:39:58 +02:00 |
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honzastor
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0f66c5a2e9
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Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
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2021-04-23 11:49:24 +02:00 |
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honzastor
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670ba45ee5
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Generated sample circuits for various representations. Updated C code circuits testing simulations and did some cleanup.
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2021-04-23 02:44:14 +02:00 |
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honzastor
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8e950fc51f
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Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
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2021-04-21 11:33:07 +02:00 |
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honzastor
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5fe150a824
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Adding possibility for automatic generation using git actions.
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2021-03-30 16:13:42 +02:00 |
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honzastor
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69e2514852
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Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
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2021-03-30 03:04:48 +02:00 |
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