diff --git a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py index 1fb1aa1..1e76475 100644 --- a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py @@ -315,8 +315,10 @@ class ArithmeticCircuit(): str: Hierarchical C code of multi-bit arithmetic circuit's function block description. """ # Obtain proper circuit name with its bit width + circuit_prefix = self.__class__( + a=Bus("a"), b=Bus("b")).prefix + str(self.N) circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus( - N=self.N, prefix="b")) + N=self.N, prefix="b"), name=circuit_prefix) return f"{circuit_block.get_circuit_c()}\n\n" def get_declarations_c_hier(self): @@ -466,8 +468,10 @@ class ArithmeticCircuit(): str: Hierarchical Verilog code of multi-bit arithmetic circuit's function block description. """ # Obtain proper circuit name with its bit width + circuit_prefix = self.__class__( + a=Bus("a"), b=Bus("b")).prefix + str(self.N) circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus( - N=self.N, prefix="b")) + N=self.N, prefix="b"), name=circuit_prefix) return f"{circuit_block.get_circuit_v()}\n\n" def get_declarations_v_hier(self): @@ -516,8 +520,10 @@ class ArithmeticCircuit(): circuit_type = self.prefix.replace(circuit_prefix+"_", "") # Obtain proper circuit name with its bit width + circuit_prefix = self.__class__( + a=Bus("a"), b=Bus("b")).prefix + str(self.N) circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus( - N=self.N, prefix="b")) + N=self.N, prefix="b"), name=circuit_prefix) return self.a.return_bus_wires_values_v_hier() + self.b.return_bus_wires_values_v_hier() + \ f" {circuit_type} {circuit_type}_{self.out.prefix}(.{circuit_block.a.prefix}({self.a.prefix}), .{circuit_block.b.prefix}({self.b.prefix}), .{circuit_block.out.prefix}({self.out.prefix}));\n" diff --git a/ariths_gen/core/arithmetic_circuits/general_circuit.py b/ariths_gen/core/arithmetic_circuits/general_circuit.py index 9f7a68e..e92bf17 100644 --- a/ariths_gen/core/arithmetic_circuits/general_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/general_circuit.py @@ -15,8 +15,11 @@ class GeneralCircuit(): that are later used for generation into various representations. """ - def __init__(self, prefix: str, out_N: int, inner_component: bool = False, inputs: list=[]): - self.prefix = prefix + def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list=[]): + if prefix == "": + self.prefix = name + else: + self.prefix = prefix + "_" + name self.inner_component = inner_component self.inputs = inputs self.out = Bus(self.prefix+"_out", out_N, out_bus=True) diff --git a/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py index e932c9f..7cf1fc9 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py @@ -117,10 +117,11 @@ class UnsignedDaddaMultiplier(MultiplierCircuit): self.out.connect(3, obj_ha.get_carry_wire()) # Final addition of remaining bits using chosen unsigned multi bit adder else: - # Create adder of final PP pairs + # Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit) + adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1) adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))]) adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))]) - final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, inner_component=True) + final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True) self.add_component(final_adder) [self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))] @@ -228,10 +229,11 @@ class SignedDaddaMultiplier(MultiplierCircuit): # Final addition of remaining bits using chosen unsigned multi bit adder else: - # Create adder of final PP pairs + # Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit) + adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1) adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))]) adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))]) - final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, inner_component=True) + final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True) self.add_component(final_adder) [self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))] diff --git a/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py index d05eeff..aa22119 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py @@ -111,10 +111,11 @@ class UnsignedWallaceMultiplier(MultiplierCircuit): self.out.connect(3, obj_ha.get_carry_wire()) # Final addition of remaining bits using chosen unsigned multi bit adder else: - # Create adder of final PP pairs + # Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit) + adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1) adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))]) adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))]) - final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, inner_component=True) + final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True) self.add_component(final_adder) [self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))] @@ -218,10 +219,11 @@ class SignedWallaceMultiplier(MultiplierCircuit): # Final addition of remaining bits using chosen unsigned multi bit adder else: - # Create adder of final PP pairs + # Obtain proper adder name with its bit width (columns bit pairs minus the first alone bit) + adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(len(self.columns)-1) adder_a = Bus(prefix=f"a", wires_list=[self.add_column_wire(column=col, bit=0) for col in range(1, len(self.columns))]) adder_b = Bus(prefix=f"b", wires_list=[self.add_column_wire(column=col, bit=1) for col in range(1, len(self.columns))]) - final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, inner_component=True) + final_adder = unsigned_adder_class_name(a=adder_a, b=adder_b, prefix=self.prefix, name=adder_name, inner_component=True) self.add_component(final_adder) [self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))] diff --git a/generate_mac.py b/generate_mac.py index 9d0d9bb..2cb69a1 100644 --- a/generate_mac.py +++ b/generate_mac.py @@ -3,26 +3,22 @@ from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCir from ariths_gen.core.arithmetic_circuits import GeneralCircuit from ariths_gen.wire_components import Bus, Wire from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder -from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier +from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier import os class MAC(GeneralCircuit): - def __init__(self, A:Bus, B:Bus, R:Bus, prefix= "mac", **kwargs): - super().__init__(prefix=prefix, out_N=2*A.N+1, inputs=[A, B, R], **kwargs) - assert A.N == B.N - assert R.N == 2 * A.N + def __init__(self, a: Bus, b: Bus, r: Bus, prefix: str = "", name: str = "mac", **kwargs): + super().__init__(prefix=prefix, name=name, out_N=2*a.N+1, inputs=[a, b, r], **kwargs) + assert a.N == b.N + assert r.N == 2 * a.N - self.mul = self.add_component(UnsignedArrayMultiplier(a=A, b=B, prefix=self.prefix, inner_component=True)) - self.add = self.add_component(UnsignedRippleCarryAdder(a=R, b=self.mul.out, prefix=self.prefix, inner_component=True)) + self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True)) + self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True)) self.out.connect_bus(connecting_bus=self.add.out) # usage os.makedirs("test_circuits/mac", exist_ok=True) -mymac = MAC(Bus("a",8), Bus("b", 8), Bus("acc", 16)) +mymac = MAC(Bus("a", 8), Bus("b", 8), Bus("acc", 16)) mymac.get_v_code_hier(open("test_circuits/mac/mac_hier.v", "w")) mymac.get_c_code_hier(open("test_circuits/mac/mac_hier.c", "w")) mymac.get_c_code_flat(open("test_circuits/mac/mac_flat.c", "w")) - -test = UnsignedRippleCarryAdder(Bus("a",8), Bus("b", 8)) -test.get_v_code_hier(open("test_circuits/urca_hier.v", "w")) -