diff --git a/.testall.sh b/.testall.sh
index e74b507..9ca3e6b 100644
--- a/.testall.sh
+++ b/.testall.sh
@@ -5,4 +5,10 @@ cd tests
 bash test_mac.sh
 bash test_circuits.sh
 bash test_circuits_verilog.sh
-bash test_circuits_cgp.sh
\ No newline at end of file
+bash test_circuits_cgp.sh
+python test_all.py
+python test_ax.py
+python test_cgp.py
+python test_compare.py
+python test_popcnt.py
+python test_reduce.py
\ No newline at end of file
diff --git a/README.md b/README.md
index a454f66..8947d28 100644
--- a/README.md
+++ b/README.md
@@ -141,6 +141,11 @@ print("Mean average error", np.abs(r - (va * vb)).mean())
 The `yosys_equiv_check.sh` script enables to formally check the equivalence of generated Verilog and BLIF representations of the same circuit.
 It uses the Yosys Open SYnthesis Suite tool by Claire Xenia Wolf. For further information, please visit: https://yosyshq.readthedocs.io/projects/yosys/en/latest/index.html.
 
+## Install Yosys
+```bash
+sudo apt-get install yosys
+```
+
 ## Execute permission
 ```bash
 chmod +x yosys_equiv_check.sh
diff --git a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py
index 2be0cf8..608550f 100644
--- a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py
+++ b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py
@@ -18,25 +18,7 @@ class ArithmeticCircuit(GeneralCircuit):
     """
 
     def __init__(self, a, b, prefix: str, name: str, out_N: int, inner_component: bool = False, one_bit_circuit: bool = False, signed: bool = False, **kwargs):
-        super().__init__(prefix, name, out_N, inner_component, inputs=[a, b], signed=signed, **kwargs)
-        if one_bit_circuit is False:
-            if prefix == "":
-                self.prefix = name
-            else:
-                self.prefix = prefix + "_" + name
-
-            self.inner_component = inner_component
-            if self.inner_component is True:
-                self.a = Bus(prefix=f"{self.prefix}_{a.prefix}", wires_list=a.bus)
-                self.b = Bus(prefix=f"{self.prefix}_{b.prefix}", wires_list=b.bus)
-
-                if a.is_output_bus():
-                    self.a.connect_bus(connecting_bus=a)
-                if b.is_output_bus():
-                    self.b.connect_bus(connecting_bus=b)
-            else:
-                self.a = Bus(prefix=f"{a.prefix}", wires_list=a.bus)
-                self.b = Bus(prefix=f"{b.prefix}", wires_list=b.bus)
+        super().__init__(prefix, name, out_N, inner_component, inputs=[a, b], signed=signed, one_bit_circuit=one_bit_circuit, **kwargs)
 
     """ C CODE GENERATION """
     def get_prototype_c(self):
diff --git a/ariths_gen/core/arithmetic_circuits/general_circuit.py b/ariths_gen/core/arithmetic_circuits/general_circuit.py
index c4fb720..94b7e89 100644
--- a/ariths_gen/core/arithmetic_circuits/general_circuit.py
+++ b/ariths_gen/core/arithmetic_circuits/general_circuit.py
@@ -18,13 +18,31 @@ class GeneralCircuit():
     that are later used for generation into various representations.
     """
 
-    def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list = [], signed: bool = False, outname=None, **kwargs):
+    def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list = [], one_bit_circuit: bool = False, signed: bool = False, outname=None, **kwargs):
         if prefix == "":
             self.prefix = name
         else:
             self.prefix = prefix + "_" + name
         self.inner_component = inner_component
-        self.inputs = inputs
+
+        if one_bit_circuit is False:
+            # Dynamic input bus assignment
+            self.inputs = []
+            input_names = "abcdefghijklmnopqrstuvwxyz"  # This should be enough..
+            assert len(input_names) >= len(inputs)
+            for i, input_bus in enumerate(inputs):
+                attr_name = input_names[i]
+                full_prefix = f"{self.prefix}_{input_bus.prefix}" if self.inner_component else f"{input_bus.prefix}"
+                bus = Bus(prefix=full_prefix, wires_list=input_bus.bus)
+                setattr(self, attr_name, bus)
+                self.inputs.append(bus)
+
+                # If the input bus is an output bus, connect it
+                if input_bus.is_output_bus():
+                    getattr(self, attr_name).connect_bus(connecting_bus=input_bus)
+        else:
+            self.inputs = inputs
+
         if not outname:
             outname = self.prefix+"_out"
         self.out = Bus(outname, out_N, out_bus=True, signed=signed)
@@ -67,7 +85,7 @@ class GeneralCircuit():
         Args:
             component: Subcomponent to be added into list of components composing described circuit.
         """
-        prefixes = [c.prefix for c in self.components]
+        prefixes = [c.prefix for c in self.components] # TODO ?
         #assert component.prefix not in prefixes, f"Component with prefix {component.prefix} already exists in the circuit."
         self.components.append(component)
         return component
@@ -388,7 +406,7 @@ class GeneralCircuit():
         """
         # Obtain proper circuit name with its bit width
         circuit_prefix = self.__class__(
-            a=Bus("a"), b=Bus("b")).prefix + str(self.N)
+            a=Bus("a", self.N), b=Bus("b", self.N)).prefix + str(self.N)
         circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(
             N=self.N, prefix="b"), name=circuit_prefix, **self._parent_kwargs)
         return f"{circuit_block.get_circuit_c()}\n\n"
@@ -433,7 +451,7 @@ class GeneralCircuit():
             str: Hierarchical C code of subcomponent's C function invocation and output assignment.
         """
         # Getting name of circuit type for proper C code generation without affecting actual generated composition
-        circuit_type = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
+        circuit_type = self.__class__(a=Bus("a", self.N), b=Bus("b", self.N)).prefix + str(self.N)
         return self.a.return_bus_wires_values_c_hier() + self.b.return_bus_wires_values_c_hier() + \
             f"  {self.out.prefix} = {circuit_type}({self.a.prefix}, {self.b.prefix});\n"
 
@@ -539,7 +557,7 @@ class GeneralCircuit():
         """
         # Obtain proper circuit name with its bit width
         circuit_prefix = self.__class__(
-            a=Bus("a"), b=Bus("b")).prefix + str(self.N)
+            a=Bus("a", self.N), b=Bus("b", self.N)).prefix + str(self.N)
         circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(
             N=self.N, prefix="b"), name=circuit_prefix, **self._parent_kwargs)
         return f"{circuit_block.get_circuit_v()}\n\n"
@@ -563,6 +581,7 @@ class GeneralCircuit():
         """
         return "".join(w.get_wire_declaration_v() for w in self.inputs + [self.out]) + "\n"
 
+        # TODO del..
         return f"  wire [{self.a.N-1}:0] {self.a.prefix};\n" + \
                f"  wire [{self.b.N-1}:0] {self.b.prefix};\n" + \
                f"  wire [{self.out.N-1}:0] {self.out.prefix};\n"
@@ -586,7 +605,7 @@ class GeneralCircuit():
             str: Hierarchical Verilog code of subcomponent's module invocation and output assignment.
         """
         # Getting name of circuit type and insitu copying out bus for proper Verilog code generation without affecting actual generated composition
-        circuit_type = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
+        circuit_type = self.__class__(a=Bus("a", self.N), b=Bus("b", self.N)).prefix + str(self.N)
         circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(
             N=self.N, prefix="b"), name=circuit_type)
         return "".join([c.return_bus_wires_values_v_hier() for c in self.inputs]) + \
@@ -692,14 +711,13 @@ class GeneralCircuit():
             str: Hierarchical Blif code of subcomponent's model invocation and output assignment.
         """
         # Getting name of circuit type for proper Blif code generation without affecting actual generated composition
-        circuit_type = self.__class__(a=Bus("a"), b=Bus("b")).prefix + str(self.N)
+        circuit_type = self.__class__(a=Bus("a", self.N), b=Bus("b", self.N)).prefix + str(self.N)
         return f"{self.a.get_wire_assign_blif(output=True)}" + \
                f"{self.b.get_wire_assign_blif(output=True)}" + \
                f".subckt {circuit_type}" + \
                "".join([f" a[{self.a.bus.index(w)}]={self.a.prefix}[{self.a.bus.index(w)}]" for w in self.a.bus]) + \
                "".join([f" b[{self.b.bus.index(w)}]={self.b.prefix}[{self.b.bus.index(w)}]" for w in self.b.bus]) + \
-               "".join(
-                   [f" {circuit_type}_out[{self.out.bus.index(o)}]={o.name}" for o in self.out.bus]) + "\n"
+               "".join([f" {circuit_type}_out[{self.out.bus.index(o)}]={o.name}" for o in self.out.bus]) + "\n"
 
     def get_circuit_blif(self):
         """Generates hierarchical Blif code subcomponent's function block.
@@ -734,7 +752,7 @@ class GeneralCircuit():
         """
         # Obtain proper circuit name with its bit width
         circuit_prefix = self.__class__(
-            a=Bus("a"), b=Bus("b")).prefix + str(self.N)
+            a=Bus("a", self.N), b=Bus("b", self.N)).prefix + str(self.N)
         circuit_block = self.__class__(a=Bus(N=self.N, prefix="a"), b=Bus(
             N=self.N, prefix="b"), name=circuit_prefix, **self._parent_kwargs)
         return f"{circuit_block.get_circuit_blif()}"
diff --git a/ariths_gen/multi_bit_circuits/approximate_multipliers/__init__.py b/ariths_gen/multi_bit_circuits/approximate_multipliers/__init__.py
index 1e5da67..0b40600 100644
--- a/ariths_gen/multi_bit_circuits/approximate_multipliers/__init__.py
+++ b/ariths_gen/multi_bit_circuits/approximate_multipliers/__init__.py
@@ -13,3 +13,12 @@ from ariths_gen.multi_bit_circuits.approximate_multipliers.broken_carry_save_mul
 from ariths_gen.multi_bit_circuits.approximate_multipliers.truncated_carry_save_multiplier import (
     UnsignedTruncatedCarrySaveMultiplier
 )
+
+from ariths_gen.multi_bit_circuits.approximate_multipliers.recursive_multiplier import (
+    UnsignedAccurateTwoBitMultiplier,
+    UnsignedApproximateTwoBitMultiplierM1,
+    UnsignedApproximateTwoBitMultiplierM2,
+    UnsignedApproximateTwoBitMultiplierM3,
+    UnsignedApproximateTwoBitMultiplierM4,
+    UnsignedRecursiveMultiplier
+)
diff --git a/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py b/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py
new file mode 100644
index 0000000..6a8ad38
--- /dev/null
+++ b/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py
@@ -0,0 +1,404 @@
+from ariths_gen.wire_components import (
+    ConstantWireValue0,
+    Bus
+)
+from ariths_gen.core.arithmetic_circuits import (
+    MultiplierCircuit
+)
+from ariths_gen.one_bit_circuits.logic_gates import (
+    AndGate,
+    OrGate,
+    XorGate,
+    NotGate
+)
+
+from ariths_gen.multi_bit_circuits.adders import (
+    UnsignedCarryLookaheadAdder
+)
+
+import math
+
+
+class UnsignedAccurateTwoBitMultiplier(MultiplierCircuit):
+    """Class representing unsigned two-bit accurate multiplier.
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of unsigned two-bit accurate multiplier. Defaults to "".
+        name (str, optional): Name of unsigned two-bit accurate multiplier. Defaults to "u_2bit_accm".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_2bit_accm", **kwargs):
+        self.N = max(a.N, b.N)
+        assert self.N == 2
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
+
+        # Bus sign extension in case buses have different lengths
+        self.a.bus_extend(N=self.N, prefix=a.prefix)
+        self.b.bus_extend(N=self.N, prefix=b.prefix)
+
+        and_obj1 = AndGate(self.a.get_wire(0), self.b.get_wire(0), prefix=self.prefix+"_and0")
+        and_obj2 = AndGate(self.a.get_wire(0), self.b.get_wire(1), prefix=self.prefix+"_and1")
+        and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and2")
+        and_obj4 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and3")
+
+        xor_obj1 = XorGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
+        and_obj5 = AndGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_and4")
+        xor_obj2 = XorGate(and_obj5.out, and_obj4.out, prefix=self.prefix+"_xor1")
+        and_obj6 = AndGate(and_obj5.out, and_obj4.out, prefix=self.prefix+"_and5")
+        [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, xor_obj1, and_obj5, xor_obj2, and_obj6]]
+
+        self.out.connect(0, and_obj1.out)
+        self.out.connect(1, xor_obj1.out)
+        self.out.connect(2, xor_obj2.out)
+        self.out.connect(3, and_obj6.out)
+
+
+class SignedAccurateTwoBitMultiplier(MultiplierCircuit):
+    """Class representing signed two-bit accurate multiplier.
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of signed two-bit accurate multiplier. Defaults to "".
+        name (str, optional): Name of signed two-bit accurate multiplier. Defaults to "s_2bit_accm".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_2bit_accm", **kwargs):
+        self.N = max(a.N, b.N)
+        raise NotImplementedError("SignedAccurateTwoBitMultiplier is not implemented yet.")
+
+
+class UnsignedApproximateTwoBitMultiplierM1(MultiplierCircuit):
+    """Class representing unsigned two-bit approximate multiplier variant M1.
+
+    M1 ax variant defined here: https://ieeexplore.ieee.org/document/8727537
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of unsigned two-bit approximate multiplier m1. Defaults to "".
+        name (str, optional): Name of unsigned two-bit approximate multiplier m1. Defaults to "u_2bit_axm1".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_2bit_axm1", **kwargs):
+        self.N = max(a.N, b.N)
+        assert self.N == 2
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
+
+        # Bus sign extension in case buses have different lengths
+        self.a.bus_extend(N=self.N, prefix=a.prefix)
+        self.b.bus_extend(N=self.N, prefix=b.prefix)
+
+        and_obj1 = AndGate(self.a.get_wire(0), self.b.get_wire(0), prefix=self.prefix+"_and0")
+        and_obj2 = AndGate(self.a.get_wire(0), self.b.get_wire(1), prefix=self.prefix+"_and1")
+        and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and2")
+        and_obj4 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and3")
+
+        or_obj1 = OrGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_or0")
+        [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, or_obj1]]
+
+        self.out.connect(0, and_obj1.out)
+        self.out.connect(1, or_obj1.out)
+        self.out.connect(2, and_obj4.out)
+        self.out.connect(3, ConstantWireValue0())
+
+
+class SignedApproximateTwoBitMultiplierM1(MultiplierCircuit):
+    """Class representing signed two-bit approximate multiplier variant M1.
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of signed two-bit approximate multiplier m1. Defaults to "".
+        name (str, optional): Name of signed two-bit approximate multiplier m1. Defaults to "s_2bit_axm1".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_2bit_axm1", **kwargs):
+        raise NotImplementedError("SignedApproximateTwoBitMultiplierM1 is not implemented yet.")
+
+
+class UnsignedApproximateTwoBitMultiplierM2(MultiplierCircuit):
+    """Class representing unsigned two-bit approximate multiplier variant M2.
+
+    M2 ax variant defined here: https://ieeexplore.ieee.org/document/8727537
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of unsigned two-bit approximate multiplier m1. Defaults to "".
+        name (str, optional): Name of unsigned two-bit approximate multiplier m1. Defaults to "u_2bit_axm1".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_2bit_axm1", **kwargs):
+        self.N = max(a.N, b.N)
+        assert self.N == 2
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
+
+        # Bus sign extension in case buses have different lengths
+        self.a.bus_extend(N=self.N, prefix=a.prefix)
+        self.b.bus_extend(N=self.N, prefix=b.prefix)
+
+        and_obj1 = AndGate(self.a.get_wire(0), self.b.get_wire(1), prefix=self.prefix+"_and0")
+        and_obj2 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and1")
+        and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and2")
+
+        and_obj4 = AndGate(and_obj1.out, and_obj2.out, prefix=self.prefix+"_and3")
+        xor_obj1 = XorGate(and_obj1.out, and_obj2.out, prefix=self.prefix+"_xor0")
+
+        xor_obj2 = XorGate(and_obj4.out, and_obj3.out, prefix=self.prefix+"_xor1")
+        [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, xor_obj1, xor_obj2]]
+
+        self.out.connect(0, and_obj4.out)
+        self.out.connect(1, xor_obj1.out)
+        self.out.connect(2, xor_obj2.out)
+        self.out.connect(3, and_obj4.out)
+
+
+class SignedApproximateTwoBitMultiplierM2(MultiplierCircuit):
+    """Class representing signed two-bit approximate multiplier variant M2.
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of signed two-bit approximate multiplier m2. Defaults to "".
+        name (str, optional): Name of signed two-bit approximate multiplier m2. Defaults to "s_2bit_axm2".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_2bit_axm2", **kwargs):
+        raise NotImplementedError("SignedApproximateTwoBitMultiplierM2 is not implemented yet.")
+
+
+class UnsignedApproximateTwoBitMultiplierM3(MultiplierCircuit):
+    """Class representing unsigned two-bit approximate multiplier variant M3.
+
+    M3 ax variant defined here: https://ieeexplore.ieee.org/document/8727537
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of unsigned two-bit approximate multiplier m3. Defaults to "".
+        name (str, optional): Name of unsigned two-bit approximate multiplier m3. Defaults to "u_2bit_axm3".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_2bit_axm3", **kwargs):
+        self.N = max(a.N, b.N)
+        assert self.N == 2
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
+
+        # Bus sign extension in case buses have different lengths
+        self.a.bus_extend(N=self.N, prefix=a.prefix)
+        self.b.bus_extend(N=self.N, prefix=b.prefix)
+
+        and_obj1 = AndGate(self.a.get_wire(0), self.b.get_wire(0), prefix=self.prefix+"_and0")
+        and_obj2 = AndGate(self.a.get_wire(0), self.b.get_wire(1), prefix=self.prefix+"_and1")
+        and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and2")
+        and_obj4 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and3")
+
+        or_obj1 = OrGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
+        not_obj1 = NotGate(and_obj1.out, prefix=self.prefix+"_not0")
+
+        and_obj5 = AndGate(not_obj1.out, and_obj4.out, prefix=self.prefix+"_and4")
+        and_obj6 = AndGate(and_obj1.out, and_obj4.out, prefix=self.prefix+"_and5")
+        [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, or_obj1, not_obj1, and_obj5, and_obj6]]
+
+        self.out.connect(0, and_obj1.out)
+        self.out.connect(1, or_obj1.out)
+        self.out.connect(2, and_obj5.out)
+        self.out.connect(3, and_obj6.out)
+
+
+class SignedApproximateTwoBitMultiplierM3(MultiplierCircuit):
+    """Class representing signed two-bit approximate multiplier variant M3.
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of signed two-bit approximate multiplier m3. Defaults to "".
+        name (str, optional): Name of signed two-bit approximate multiplier m3. Defaults to "s_2bit_axm3".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_2bit_axm3", **kwargs):
+        raise NotImplementedError("SignedApproximateTwoBitMultiplierM3 is not implemented yet.")
+
+
+class UnsignedApproximateTwoBitMultiplierM4(MultiplierCircuit):
+    """Class representing unsigned two-bit approximate multiplier variant M4.
+
+    M4 ax variant defined here: https://ieeexplore.ieee.org/document/8727537
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of unsigned two-bit approximate multiplier m4. Defaults to "".
+        name (str, optional): Name of unsigned two-bit approximate multiplier m4. Defaults to "u_2bit_axm4".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_2bit_axm4", **kwargs):
+        self.N = max(a.N, b.N)
+        assert self.N == 2
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
+
+        # Bus sign extension in case buses have different lengths
+        self.a.bus_extend(N=self.N, prefix=a.prefix)
+        self.b.bus_extend(N=self.N, prefix=b.prefix)
+
+        and_obj1 = AndGate(self.a.get_wire(0), self.b.get_wire(0), prefix=self.prefix+"_and0")
+        and_obj2 = AndGate(self.a.get_wire(0), self.b.get_wire(1), prefix=self.prefix+"_and1")
+        and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and2")
+        and_obj4 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and3")
+
+        xor_obj1 = XorGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
+        [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, xor_obj1]]
+
+        self.out.connect(0, and_obj1.out)
+        self.out.connect(1, xor_obj1.out)
+        self.out.connect(2, and_obj4.out)
+        self.out.connect(3, ConstantWireValue0())
+
+
+class SignedApproximateTwoBitMultiplierM4(MultiplierCircuit):
+    """Class representing signed two-bit approximate multiplier variant M4.
+
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of signed two-bit approximate multiplier m4. Defaults to "".
+        name (str, optional): Name of signed two-bit approximate multiplier m4. Defaults to "s_2bit_axm4".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_2bit_axm4", **kwargs):
+        raise NotImplementedError("SignedApproximateTwoBitMultiplierM4 is not implemented yet.")
+
+
+class UnsignedRecursiveMultiplier(MultiplierCircuit):
+    """Class representing unsigned recursive multiplier.
+
+    TODO
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of unsigned recursive multiplier. Defaults to "".
+        name (str, optional): Name of unsigned recursive multiplier. Defaults to "u_rm".
+        submultipliers (list[MultiplierCircuit], optional): List of submultipliers.
+                        Defaults (if None) to the required number of UnsignedAccurateTwoBitMultiplier instances.
+        unsigned_adder_class_name (str, optional): Unsigned multi bit adder used to obtain final sums of products. Defaults to UnsignedCarryLookaheadAdder.
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "u_rm", submultipliers: list[MultiplierCircuit] = None, unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs):
+        self.N = max(a.N, b.N)
+        assert self.N > 1 and self.N & (self.N-1) == 0  # assure that N is a power of two greater than 1 (So allowed N is 2, 4, 8, ..)
+        super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, **kwargs)
+
+        # Bus sign extension in case buses have different lengths
+        self.a.bus_extend(N=self.N, prefix=a.prefix)
+        self.b.bus_extend(N=self.N, prefix=b.prefix)
+
+        if submultipliers is None:  # By default, we assume composition from accurate two bit submultipliers
+            if self.N == 2:
+                submultipliers = [UnsignedAccurateTwoBitMultiplier]
+            else:
+                submultipliers = [UnsignedAccurateTwoBitMultiplier for _ in range((self.N//2)**2)]
+
+        assert (self.N > 2 and len(submultipliers) == (self.N//2)**2) or (self.N == 2 and len(submultipliers) == 1)
+
+        if self.N == 2: # Base case for just one two-bit multiplier
+            # TODO add suffix in ariths_gen rework
+            mult = submultipliers[0](Bus(prefix=self.prefix + "_a", wires_list=self.a.bus), Bus(prefix=self.prefix + "_b", wires_list=self.b.bus), prefix=self.prefix + "_" + str(self.get_instance_num(cls=submultipliers[0])), **kwargs)
+            self.add_component(mult)
+            self.out.connect_bus(mult.out)
+        else:
+            # Levels of construction of the recursive multiplier
+            # recursive_levels = int(math.log2(self.N)-1)  # Number of recursive levels based on the power ith power of 2 (e.g. for N=8, we have 2 recursive levels)
+            block_level = 1
+            partial_products = []
+
+            for m in range(len(submultipliers)):  # Iterate over all 2-bit submultipliers (equals range(0, 4**recursive_levels))
+                a_bus_offset = 0
+                b_bus_offset = 0
+                curr_level = block_level
+                curr_id = m
+
+                # Determine the wires offsets from MSB (for input bus `a` and `b`) for the current 2-bit submultiplier
+                # There is a pattern, for example for N=8, we have 16 two-bit submultipliers with offsets:
+                #       Mult ID:  1  2  3  4   5  6  7  8   9 10 11 12   13 14 15 16
+                # MSB a_offsets:  0  0  2  2   0  0  2  2   4  4  6  6    4  4  6  6
+                # MSB b_offsets:  0  2  0  2   4  6  4  6   0  2  0  2    4  6  4  6
+                while curr_level != 0:
+                    # A offset
+                    if curr_id // ((4**curr_level)//2) != 0:
+                        a_bus_offset += 2**curr_level
+
+                    # B offset
+                    if (curr_id // ((4**curr_level)//4)) % 2 != 0:
+                        b_bus_offset += 2**curr_level
+
+                    curr_level -= 1
+                    curr_id -= (4**curr_level)*((curr_id // (4**curr_level)))
+
+                # Create 2-bit submultiplier with the corresponding input bits
+                # TODO add suffix in ariths_gen rework
+                submult_a_bus = Bus(prefix=f"mult{m}_a", wires_list=self.a.bus[::-1][0+a_bus_offset:0+a_bus_offset+2][::-1], N=2)
+                submult_b_bus = Bus(prefix=f"mult{m}_b", wires_list=self.b.bus[::-1][0+b_bus_offset:0+b_bus_offset+2][::-1], N=2)
+                submult = submultipliers[m](submult_a_bus, submult_b_bus, prefix=self.prefix + "_" + str(self.get_instance_num(cls=submultipliers[m])))
+                self.add_component(submult)
+
+                # Create wire vectors holding partial products for final summation
+                pp = Bus(prefix=f"pp_{m}", N=self.out.N, wires_list=[ConstantWireValue0() for _ in range(self.out.N)])
+                #[pp.connect_bus(submult.out, offset=(self.out.N-4)-(a_bus_offset+b_bus_offset))]
+                [pp.connect((self.out.N-1)-(a_bus_offset+b_bus_offset)-i, submult.out[3-i], inserted_wire_desired_index=3-i) for i in range(4)]
+                partial_products.append(pp)
+
+                # Distinction of levels of blocks to properly instantiate and connect 2-bit submultipliers
+                # For example, for N=8, we have 4 two-bit submultipliers in the first level, but then we have 4 times the
+                # same structure (4 two-bit mults) as the base component for the second level, similarly for N=16, but
+                # with additional third layer (consisting of 16 two-bit submultipliers)
+                if (m+1) % (4**block_level) == 0:
+                    block_level += 1  # Increase the block level
+
+            # Create tree of partial product adders
+            while len(partial_products) != 1:
+                N = len(partial_products)//2
+                # Creation of composite unsigned multi bit adders from set of partial product vectors and addition of generated blocks outputs for next iteration
+                for bus_index in range(0, N):
+                    # TODO arithsgen_rework: update check for bus declaration and assignment (if true do declare/assign again - here we would not create new bus, just assign the existing one); it should create cleaner outcode with unncecessary new bus declarations
+                    adder_name = unsigned_adder_class_name(a=a, b=b).prefix + str(self.get_instance_num(cls=unsigned_adder_class_name))
+                    # TODO rework the buses
+                    bus_a = Bus(prefix=f"{adder_name}_a", wires_list=partial_products[bus_index].bus, out_bus=True) if partial_products[bus_index].out_bus else partial_products[bus_index]
+                    bus_b = Bus(prefix=f"{adder_name}_b", wires_list=partial_products[bus_index+N].bus, out_bus=True) if partial_products[bus_index+N].out_bus else partial_products[bus_index+N]
+                    adder = unsigned_adder_class_name(a=bus_a, b=bus_b, prefix=self.prefix, name=adder_name, inner_component=True, **kwargs)
+                    self.add_component(adder)
+                    partial_products.append(adder.out)
+
+                # Update partial products list for next iteration until it contains only one output vector
+                partial_products = partial_products[2*N:]
+            # Connect the final output of the recursive multiplier
+            self.out.connect_bus(partial_products[0])
+
+
+class SignedRecursiveMultiplier(MultiplierCircuit):
+    """Class representing signed recursive multiplier.
+
+    TODO
+    Description of the __init__ method.
+
+    Args:
+        a (Bus): First input bus.
+        b (Bus): Second input bus.
+        prefix (str, optional): Prefix name of signed recursive multiplier. Defaults to "".
+        name (str, optional): Name of signed recursive multiplier. Defaults to "s_rm".
+    """
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_rm", **kwargs):
+        raise NotImplementedError("SignedRecursiveMultiplier is not implemented yet.")
diff --git a/ariths_gen/wire_components/wires.py b/ariths_gen/wire_components/wires.py
index c34240b..8a68d1e 100644
--- a/ariths_gen/wire_components/wires.py
+++ b/ariths_gen/wire_components/wires.py
@@ -99,7 +99,7 @@ class Wire():
         if self.is_const():
             return f"({self.c_const}) << {offset};\n"
         else:
-            return f"(({self.prefix} >> {self.index}) & 0x01ull) << {offset};\n"
+            return f"(({self.name} >> 0) & 0x01ull) << {offset};\n"
 
     def return_wire_value_c_hier(self, offset: int = 0):
         """Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for hierarchical generation.
diff --git a/generate_quad_lib.py b/generate_quad_lib.py
index 1395ab0..8d7c62a 100644
--- a/generate_quad_lib.py
+++ b/generate_quad_lib.py
@@ -16,6 +16,7 @@ import itertools
 
 if __name__ == "__main__":
 
+    N = 8
     directory = f"lib_quad/lib_quad{N}"
     os.makedirs(directory, exist_ok=True)
 
@@ -30,7 +31,6 @@ if __name__ == "__main__":
     import zipfile
     vfile = zipfile.ZipFile(file=f"{directory}/lib_quad_{N}.zip", mode="w", compression=zipfile.ZIP_DEFLATED)
     cnt = 0
-    N = 8
 
     # up to 3 stages
     for n in [1, 2, 3]:
diff --git a/generate_test.py b/generate_test.py
index b8b5a0f..6d1ebd9 100644
--- a/generate_test.py
+++ b/generate_test.py
@@ -65,6 +65,11 @@ from ariths_gen.multi_bit_circuits.multipliers import (
     SignedCarrySaveMultiplier
 )
 
+from ariths_gen.multi_bit_circuits.approximate_multipliers import (
+    UnsignedRecursiveMultiplier,
+    UnsignedAccurateTwoBitMultiplier
+)
+
 from ariths_gen.multi_bit_circuits.dividers import (
     ArrayDivider
 )
@@ -226,6 +231,11 @@ if __name__ == "__main__":
         name = f"s_arrmul{N}"
         circuit = SignedArrayMultiplier(a, b, name=name)
         export_circuit(circuit, name)
+        
+        # Accurate recursive multiplier
+        name = f"u_recmul{N}"
+        circuit = UnsignedRecursiveMultiplier(a, b, name=name)
+        export_circuit(circuit, name)
 
         # Csamul (Braun multiplier) – the ppa adders are also configurable as above if desirable
         name = f"u_csamul_cla{N}"
diff --git a/tests/test_all.py b/tests/test_all.py
index c8cd777..33af3c1 100644
--- a/tests/test_all.py
+++ b/tests/test_all.py
@@ -1,3 +1,11 @@
+import os
+import sys
+# Add the parent directory to the system path
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+import numpy as np
+import math
+
 from ariths_gen.wire_components import (
     Wire,
     ConstantWireValue0,
@@ -51,7 +59,9 @@ from ariths_gen.multi_bit_circuits.approximate_multipliers import (
     UnsignedTruncatedArrayMultiplier,
     UnsignedTruncatedCarrySaveMultiplier,
     UnsignedBrokenArrayMultiplier,
-    UnsignedBrokenCarrySaveMultiplier
+    UnsignedBrokenCarrySaveMultiplier,
+    UnsignedRecursiveMultiplier,
+    UnsignedAccurateTwoBitMultiplier
 )
 
 from ariths_gen.one_bit_circuits.logic_gates import (
@@ -63,8 +73,6 @@ from ariths_gen.one_bit_circuits.logic_gates import (
     XnorGate,
     NotGate
 )
-import numpy as np
-import math
 
 
 def test_unsigned_approxmul(values=False):
@@ -120,6 +128,19 @@ def test_unsigned_mul():
         assert mul(0, 0) == 0
         r = mul(av, bv)
         np.testing.assert_array_equal(expected, r)
+    
+    # Accurate variant of recursive multiplier
+    for c in [UnsignedRecursiveMultiplier]:
+        N_rec = 8
+        a_rec = Bus(N=N_rec, prefix="a")
+        b_rec = Bus(N=N_rec, prefix="b")
+        av_rec = np.arange(2**N_rec)
+        bv_rec = av_rec.reshape(-1, 1)
+        expected_rec = av_rec * bv_rec
+        mul = c(a_rec, b_rec, submultipliers=[UnsignedAccurateTwoBitMultiplier for _ in range((N_rec//2)**2)])
+        assert mul(0, 0) == 0
+        r = mul(av_rec, bv_rec)
+        np.testing.assert_array_equal(expected_rec, r)
 
     # Configurable PPA
     for c in [UnsignedDaddaMultiplier, UnsignedCarrySaveMultiplier, UnsignedWallaceMultiplier]:
@@ -342,6 +363,7 @@ def test_direct():
     np.testing.assert_equal(r, expected)
     print(r)
 
+
 def test_wire_as_bus():
     """ accept a wire as a bus """
     class test_circuit(GeneralCircuit):
@@ -353,8 +375,20 @@ def test_wire_as_bus():
             self.out[0] = g3.out
 
     circ = test_circuit(Wire("a"), Wire("b"), Bus("c", 2), "c1")
-    r = circ(np.array([0, 1]), 
-        np.array([0, 1]).reshape(-1, 1), 
-        np.arange(4).reshape(-1, 1, 1))
+    r = circ(np.array([0, 1]),
+             np.array([0, 1]).reshape(-1, 1),
+             np.arange(4).reshape(-1, 1, 1))
     assert r.sum() == 1
-    assert r[-1, -1, -1] == 1
\ No newline at end of file
+    assert r[-1, -1, -1] == 1
+
+
+if __name__ == "__main__":
+    test_unsigned_approxmul()
+    test_unsigned_mul()
+    test_signed_mul()
+    test_unsigned_add()
+    test_signed_add()
+    test_mac()
+    test_direct()
+    test_wire_as_bus()
+    print("Python tests were successful!")
diff --git a/tests/test_ax.py b/tests/test_ax.py
index b78b8fe..a833fe7 100644
--- a/tests/test_ax.py
+++ b/tests/test_ax.py
@@ -1,21 +1,26 @@
 """
 Testing the QuAdder
 """
+import os
+import sys
+# Add the parent directory to the system path
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+import numpy as np
+import itertools
+
 from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
 from ariths_gen.core.arithmetic_circuits import GeneralCircuit
 from ariths_gen.wire_components import Bus, Wire
 from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
 from ariths_gen.multi_bit_circuits.approximate_adders import QuAdder
 from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier
-import os, sys
 
-import numpy as np
-import itertools
 
 def test_quadder():
-    c = QuAdder(Bus("a", 8), Bus("b", 8), R = [4, 2, 2], P=[0, 2, 2], prefix="quad")
+    c = QuAdder(Bus("a", 8), Bus("b", 8), R=[4, 2, 2], P=[0, 2, 2], prefix="quad")
     c.get_v_code_hier(file_object=sys.stdout)
-    
+
     x = np.arange(0, 256).reshape(-1, 1)
     y = np.arange(0, 256).reshape(1, -1)
 
@@ -23,4 +28,9 @@ def test_quadder():
     r2 = x + y
 
     assert np.abs(r - r2).max() == 64
-    np.testing.assert_equal(np.abs(r - r2).mean(), 7.5)
\ No newline at end of file
+    np.testing.assert_equal(np.abs(r - r2).mean(), 7.5)
+
+
+if __name__ == "__main__":
+    test_quadder()
+    print("Quadder Python tests were successful!")
diff --git a/tests/test_cgp.py b/tests/test_cgp.py
index 26f66e4..dd1cb3a 100644
--- a/tests/test_cgp.py
+++ b/tests/test_cgp.py
@@ -1,3 +1,13 @@
+import os
+import sys
+# Add the parent directory to the system path
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+
+import numpy as np
+import math
+from io import StringIO
+
 from ariths_gen.wire_components import (
     Wire,
     ConstantWireValue0,
@@ -57,10 +67,6 @@ from ariths_gen.multi_bit_circuits.approximate_multipliers import (
 
 from ariths_gen.core.cgp_circuit import UnsignedCGPCircuit, SignedCGPCircuit
 
-import numpy as np
-import math
-from io import StringIO
-
 
 def test_cgp_unsigned_add():
     """ Test unsigned adders """
@@ -199,7 +205,7 @@ def test_cgp_signed_add():
             np.testing.assert_array_equal(expected, r)
 
 
-def test_unsigned_mul():
+def test_cgp_unsigned_mul():
     """ Test unsigned multipliers """
     N = 7
     a = Bus(N=N, prefix="a")
@@ -311,7 +317,7 @@ def test_unsigned_mul():
                 np.testing.assert_array_equal(expected, r)
 
 
-def test_signed_mul():
+def test_cgp_signed_mul():
     """ Test signed multipliers """
     N = 7
     a = Bus(N=N, prefix="a")
@@ -429,3 +435,12 @@ def test_cgp_variant1():
 
     c = UnsignedCGPCircuit(cgp, [8, 8], name="cgp_circuit")
     assert c(0, 0) == 8  # TypeError: 'int' object is not subscriptable
+
+
+if __name__ == "__main__":
+    test_cgp_unsigned_add()
+    test_cgp_signed_add()
+    test_cgp_unsigned_mul()
+    test_cgp_signed_mul()
+    test_cgp_variant1()
+    print("CGP Python tests were successful!")
diff --git a/tests/test_circuits.sh b/tests/test_circuits.sh
index e6a5af7..0dda0d4 100755
--- a/tests/test_circuits.sh
+++ b/tests/test_circuits.sh
@@ -109,6 +109,7 @@ test_circuit "multiplier_signed" "s_dadda_lfa8"
 
 
 test_circuit "multiplier_unsigned" "u_arrmul8"
+test_circuit "multiplier_unsigned" "u_recmul8"
 test_circuit "multiplier_unsigned" "u_csamul_cla8" 
 test_circuit "multiplier_unsigned" "u_csamul_rca8" 
 test_circuit "multiplier_unsigned" "u_csamul_pg_rca8" 
@@ -253,6 +254,7 @@ fi
 # exporting u_ka8
 # exporting u_lfa8
 # exporting u_arrmul8
+# exporting u_recmul8
 # exporting u_csamul_cla8"
 # exporting u_csamul_rca8"
 # exporting u_csamul_pg_rca8"
diff --git a/tests/test_circuits_cgp.sh b/tests/test_circuits_cgp.sh
index f291e75..005b4b4 100755
--- a/tests/test_circuits_cgp.sh
+++ b/tests/test_circuits_cgp.sh
@@ -113,6 +113,7 @@ test_circuit "multiplier_signed" "s_dadda_lfa8"
 
 
 test_circuit "multiplier_unsigned" "u_arrmul8"
+test_circuit "multiplier_unsigned" "u_recmul8"
 test_circuit "multiplier_unsigned" "u_csamul_cla8" 
 test_circuit "multiplier_unsigned" "u_csamul_rca8" 
 test_circuit "multiplier_unsigned" "u_csamul_pg_rca8" 
diff --git a/tests/test_circuits_verilog.sh b/tests/test_circuits_verilog.sh
index 948e8ec..37b56e2 100644
--- a/tests/test_circuits_verilog.sh
+++ b/tests/test_circuits_verilog.sh
@@ -122,6 +122,7 @@ test_circuit "multiplier_signed" "s_dadda_lfa8"
 
 
 test_circuit "multiplier_unsigned" "u_arrmul8"
+test_circuit "multiplier_unsigned" "u_recmul8"
 test_circuit "multiplier_unsigned" "u_csamul_cla8" 
 test_circuit "multiplier_unsigned" "u_csamul_rca8" 
 test_circuit "multiplier_unsigned" "u_csamul_pg_rca8" 
diff --git a/tests/test_compare.py b/tests/test_compare.py
index 02e1312..9375887 100644
--- a/tests/test_compare.py
+++ b/tests/test_compare.py
@@ -1,3 +1,13 @@
+import os
+import sys
+# Add the parent directory to the system path
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+
+import numpy as np
+import math
+from io import StringIO
+
 from ariths_gen.wire_components import (
     Wire,
     ConstantWireValue0,
@@ -11,10 +21,6 @@ from ariths_gen.multi_bit_circuits.others import (
     UnsignedCompareLT
 )
 
-import numpy as np
-import math
-from io import StringIO
-
 
 def test_compare():
     """ Test unsigned comparator """
@@ -47,4 +53,6 @@ def test_compare():
     np.testing.assert_array_equal(v, expected)
 
 
-    
\ No newline at end of file
+if __name__ == "__main__":
+    test_compare()
+    print("Python compare tests were successful!")
\ No newline at end of file
diff --git a/tests/test_popcnt.py b/tests/test_popcnt.py
index 8d66628..85bf55c 100644
--- a/tests/test_popcnt.py
+++ b/tests/test_popcnt.py
@@ -1,3 +1,13 @@
+import os
+import sys
+# Add the parent directory to the system path
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+
+import numpy as np
+import math
+from io import StringIO
+
 from ariths_gen.wire_components import (
     Wire,
     ConstantWireValue0,
@@ -11,10 +21,6 @@ from ariths_gen.multi_bit_circuits.others import (
     UnsignedPopCount
 )
 
-import numpy as np
-import math
-from io import StringIO
-
 
 def test_popcount():
     """ Test unsigned adders """
@@ -47,4 +53,6 @@ def test_popcount():
         np.testing.assert_array_equal(popcnt(av), expected)
 
 
-    
\ No newline at end of file
+if __name__ == "__main__":
+    test_popcount()
+    print("Python popcnt tests were successful!")
diff --git a/tests/test_reduce.py b/tests/test_reduce.py
index 9ec4b7e..b93e7c0 100644
--- a/tests/test_reduce.py
+++ b/tests/test_reduce.py
@@ -1,3 +1,13 @@
+import os
+import sys
+# Add the parent directory to the system path
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+
+import numpy as np
+import math
+from io import StringIO
+
 from ariths_gen.wire_components import (
     Wire,
     ConstantWireValue0,
@@ -8,13 +18,11 @@ from ariths_gen.wire_components import (
 from ariths_gen.core.arithmetic_circuits import GeneralCircuit
 
 from ariths_gen.multi_bit_circuits.others import (
-    BitReduce, AndReduce, OrReduce
+    BitReduce,
+    AndReduce,
+    OrReduce
 )
 
-import numpy as np
-import math
-from io import StringIO
-
 
 def test_orreduce():
     """ Test unsigned adders """
@@ -75,4 +83,8 @@ def test_andreduce():
 
         np.testing.assert_array_equal(reduce(av), expected)
 
-    
\ No newline at end of file
+
+if __name__ == "__main__":
+    test_andreduce()
+    test_orreduce()
+    print("Python reduce tests were successful!")