From cfb5bba3ecc35df654089f0646307fc78ddb60fc Mon Sep 17 00:00:00 2001 From: honzastor Date: Sun, 10 Oct 2021 00:02:58 +0200 Subject: [PATCH] Bitwise and operation fix. --- ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py | 4 ++-- .../core/one_bit_circuits/three_input_one_bit_circuit.py | 2 +- .../core/one_bit_circuits/two_input_one_bit_circuit.py | 2 +- ariths_gen/wire_components/wires.py | 8 ++++---- chr2c.py | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py b/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py index 9594bc2..eac7a40 100644 --- a/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py +++ b/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py @@ -526,7 +526,7 @@ class TwoInputInvertedLogicGate(TwoInputLogicGate): Returns: str: C code description of negated logic gate's Boolean function (with bitwise shifted inputs). """ - return "~("+(super().get_function_c()) + ") & 0x01ull" + return "~("+(super().get_function_c()) + ") & 0x01" """ VERILOG CODE GENERATION """ # FLAT VERILOG # @@ -586,7 +586,7 @@ class OneInputLogicGate(TwoInputLogicGate): Returns: str: C code description of logic gate's Boolean function (with bitwise shifted input). """ - return f"{self.operator}({self.a.get_wire_value_c_flat()}) & 0x01ull" + return f"{self.operator}({self.a.get_wire_value_c_flat()}) & 0x01" # HIERARCHICAL C # def get_prototype_c_hier(self): diff --git a/ariths_gen/core/one_bit_circuits/three_input_one_bit_circuit.py b/ariths_gen/core/one_bit_circuits/three_input_one_bit_circuit.py index d2a1fa5..a552d59 100644 --- a/ariths_gen/core/one_bit_circuits/three_input_one_bit_circuit.py +++ b/ariths_gen/core/one_bit_circuits/three_input_one_bit_circuit.py @@ -50,7 +50,7 @@ class ThreeInputOneBitCircuit(TwoInputOneBitCircuit): output_bus_wire_names = [] [output_bus_wire_names.append(w.prefix) for w in self.out.bus] circuit_block = self.__class__() - return "".join([f" {c.out.prefix} = ({circuit_block.prefix}({self.a.get_wire_value_c_hier()}, {self.b.get_wire_value_c_hier()}, {self.c.get_wire_value_c_hier()}) >> {output_bus_wire_names.index(c.out.prefix)}) & 0x01ull;\n" for c in self.components if c.disable_generation is False and c.out.prefix in output_bus_wire_names]) + return "".join([f" {c.out.prefix} = ({circuit_block.prefix}({self.a.get_wire_value_c_hier()}, {self.b.get_wire_value_c_hier()}, {self.c.get_wire_value_c_hier()}) >> {output_bus_wire_names.index(c.out.prefix)}) & 0x01;\n" for c in self.components if c.disable_generation is False and c.out.prefix in output_bus_wire_names]) """ VERILOG CODE GENERATION """ # FLAT VERILOG # diff --git a/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py b/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py index 022bde5..c630058 100644 --- a/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py +++ b/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py @@ -66,7 +66,7 @@ class TwoInputOneBitCircuit(ArithmeticCircuit): output_bus_wire_names = [] [output_bus_wire_names.append(w.prefix) for w in self.out.bus] circuit_block = self.__class__() - return "".join([f" {c.out.prefix} = ({circuit_block.prefix}({self.a.get_wire_value_c_hier()}, {self.b.get_wire_value_c_hier()}) >> {output_bus_wire_names.index(c.out.prefix)}) & 0x01ull;\n" for c in self.components if c.disable_generation is False and c.out.prefix in output_bus_wire_names]) + return "".join([f" {c.out.prefix} = ({circuit_block.prefix}({self.a.get_wire_value_c_hier()}, {self.b.get_wire_value_c_hier()}) >> {output_bus_wire_names.index(c.out.prefix)}) & 0x01;\n" for c in self.components if c.disable_generation is False and c.out.prefix in output_bus_wire_names]) # Self circuit hierarchical generation def get_declaration_c_hier(self): diff --git a/ariths_gen/wire_components/wires.py b/ariths_gen/wire_components/wires.py index 9afeef0..be77fcc 100644 --- a/ariths_gen/wire_components/wires.py +++ b/ariths_gen/wire_components/wires.py @@ -65,9 +65,9 @@ class Wire(): # If wire is part of an input bus (where wire names are concatenated from bus prefix and their index position inside the bus in square brackets) # then the wire value is obtained from bitwise shifting the required wire from the parent bus ('parent_bus.prefix' is the same value as 'self.prefix') if self.name.endswith("["+str(self.index)+"]") and self.parent_bus is not None: - return f"(({self.prefix} >> {self.index}) & 0x01ull)" + return f"(({self.prefix} >> {self.index}) & 0x01)" else: - return f"(({self.name} >> 0) & 0x01ull)" + return f"(({self.name} >> 0) & 0x01)" def get_wire_value_c_hier(self): """Accesses desired bit value from wire represented in C code variable used for hierarchical generation. @@ -78,7 +78,7 @@ class Wire(): if self.is_const(): return f"({self.c_const})" else: - return f"(({self.prefix} >> {self.index}) & 0x01ull)" + return f"(({self.prefix} >> {self.index}) & 0x01)" def return_wire_value_c_flat(self, offset: int = 0): """Retrieves desired bit value from wire represented in C code variable and bitwise shifts it to desired position for storing it within a bus for flat generation. @@ -290,7 +290,7 @@ class ConstantWireValue1(Wire): self.value = 1 self.parent_bus = None - self.c_const = "0x01ull" + self.c_const = "0x01" self.v_const = "1'b1" self.blif_const = "vdd" # Constant wire id for CGP generation diff --git a/chr2c.py b/chr2c.py index 0f39a66..66fb2c0 100644 --- a/chr2c.py +++ b/chr2c.py @@ -126,7 +126,7 @@ def parse_chromosome(chromosome, signed=False, function=None): # Export converted outputs into C code function body for i in range(0, c_out): if outs[i] in trans: - lines_end.append(" y |= (%s & 0x01) << %d; // default output" % (trans[outs[i]], i)) + lines_end.append(" y |= (%s & 0x01ull) << %d; // default output" % (trans[outs[i]], i)) else: assert False