diff --git a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py index e11a5f6..d4d664f 100644 --- a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py +++ b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py @@ -35,6 +35,9 @@ class UnsignedCarryLookaheadAdder(ArithmeticCircuit): of more complex circuitry but provides much less propagation delay as opposed to rca. It is mainly composed of propagate/generate blocks and many AND/OR gates to calculate carries individually. + Class enables to choose the size of composite inner cla blocks (default is 4). These cla blocks are then cascaded + to form the final N bit adder. + ``` B3 A3 B2 A2 B1 A1 B0 A0 │ │ │ │ │ │ │ │ @@ -58,10 +61,10 @@ class UnsignedCarryLookaheadAdder(ArithmeticCircuit): Args: a (Bus): First input bus. b (Bus): Second input bus. + cla_block_size (int, optional): Size of each composite cla adder block size. Defaults to 4. prefix (str, optional): Prefix name of unsigned cla. Defaults to "u_cla". """ def __init__(self, a: Bus, b: Bus, cla_block_size: int = 4, prefix: str = "u_cla"): - #TODO super().__init__() self.N = max(a.N, b.N) self.prefix = prefix @@ -143,7 +146,6 @@ class UnsignedCarryLookaheadAdder(ArithmeticCircuit): N_wires -= block_size N_blocks += 1 - # Connection of final Cout self.out.connect(self.N, cin) @@ -154,6 +156,9 @@ class SignedCarryLookaheadAdder(UnsignedCarryLookaheadAdder, ArithmeticCircuit): Signed carry-lookahead adder represents faster adder circuit which is composed of more complex circuitry but provides much less propagation delay as opposed to rca. It is mainly composed of propagate/generate blocks and many AND/OR gates to calculate carries individually. + + Class enables to choose the size of composite inner cla blocks (default is 4). These cla blocks are then cascaded + to form the final N bit adder. At last XOR gates are used to ensure proper sign extension. ``` @@ -179,6 +184,7 @@ class SignedCarryLookaheadAdder(UnsignedCarryLookaheadAdder, ArithmeticCircuit): Args: a (Bus): First input bus. b (Bus): Second input bus. + cla_block_size (int, optional): Size of each composite cla adder block size. Defaults to 4. prefix (str, optional): Prefix name of signed cla. Defaults to "s_cla". """ def __init__(self, a: Bus, b: Bus, cla_block_size: int = 4, prefix: str = "s_cla"): diff --git a/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py index d6da667..7c95edc 100644 --- a/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py +++ b/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py @@ -35,7 +35,7 @@ class UnsignedCarrySkipAdder(ArithmeticCircuit): Unsigned carry skip (bypass) adder represents faster adder circuit which is composed of more complex circuitry but provides much less propagation delay as opposed to rca. - + Each carry bypass block is composed of these logic parts: Propagate XOR gates compute propagate signals of corresponding bit pairs, these signals are then combined in multiple input AND gate (cascaded two input gates). @@ -44,22 +44,23 @@ class UnsignedCarrySkipAdder(ArithmeticCircuit): Finally multiplexer lies at the end of each carry bypass block and is used to propagate block's input carry if multiple input AND gate output, which serves as select signal, is 1 or to wait for rippling of cout from the block's adders if it is 0. - ```TODO - B3 A3 B2 A2 B1 A1 B0 A0 - │ │ │ │ │ │ │ │ - ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ - │ PG │ │ PG │ │ PG │ │ PG │ - │ block│ │ block│ │ block│ │ block│ - │ │ │ │ │ │ │ │ - └─┬┬┬──┘ └─┬┬┬──┘ └─┬┬┬──┘ └─┬┬┬──┘ - │││G3P3S3 │││G2P2S2 │││G1P1S1 │││G0P0S0 - ┌─▼▼▼────────▼▼▼────────▼▼▼────────▼▼▼──┐ - │ Carry Lookahead logic │ - │ │ - └┬────┬───────┬──────────┬──────────┬───┘ - │ │ │ │ │ - ▼ ▼ ▼ ▼ ▼ - Cout S3 S1 S0 S0 + ``` + ┼ ┼ ┼ ┼ + ┌───▼───▼───┐ ┌───▼───▼───┐ + ┌────┤ Propagate │ ┌────┤ Propagate │ + │SEL │ signals │ │SEL │ signals │ + ┌────▼─┐ └───────────┘ ┌────▼─┐ └───────────┘ + │ │ │ │ + ┌──┤2:1MUX│◄────────────────┬─┤2:1MUX│◄────────────────┬─Cin + │ │ │ │ │ │ │ + │ └────▲─┘ ┼ ┼ │ └────▲─┘ ┼ ┼ │ + │ │ ┌───▼───▼───┐ │ │ ┌───▼───▼───┐ │ + │ │ │ Adders │◄─┘ │ │ Adders │◄─┘ + │ └────┤ │ └────┤ │ + │ └─────┬─────┘ └─────┬─────┘ + │ │ │ + ▼ ▼ ▼ + Cout Sums Sums ``` Description of the __init__ method. @@ -103,7 +104,7 @@ class UnsignedCarrySkipAdder(ArithmeticCircuit): obj_adder = HalfAdder(a=self.a.get_wire((N_blocks*bypass_block_size)+i), b=self.b.get_wire((N_blocks*bypass_block_size)+i), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder))) else: obj_adder = FullAdder(a=self.a.get_wire((N_blocks*bypass_block_size)+i), b=self.b.get_wire((N_blocks*bypass_block_size)+i), c=cout, prefix=self.prefix+"_fa"+str(self.get_instance_num(cls=FullAdder))) - + cout = obj_adder.get_carry_wire() self.add_component(obj_adder) # Connecting adder's output sum bit to its proper position within the described circuit's output bus @@ -131,7 +132,7 @@ class SignedCarrySkipAdder(UnsignedCarrySkipAdder, ArithmeticCircuit): Signed carry skip (bypass) adder represents faster adder circuit which is composed of more complex circuitry but provides much less propagation delay as opposed to rca. - + Each carry bypass block is composed of these logic parts: Propagate XOR gates compute propagate signals of corresponding bit pairs, these signals are then combined in multiple input AND gate (cascaded two input gates). @@ -139,25 +140,26 @@ class SignedCarrySkipAdder(UnsignedCarrySkipAdder, ArithmeticCircuit): additionally these adders compute individual output sum bits. Finally multiplexer lies at the end of each carry bypass block and is used to propagate block's input carry if multiple input AND gate output, which serves as select signal, is 1 or to wait for rippling of cout from the block's adders if it is 0. - + At last XOR gates are used to ensure proper sign extension. - ```TODO - B3 A3 B2 A2 B1 A1 B0 A0 - │ │ │ │ │ │ │ │ - ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ - │ PG │ │ PG │ │ PG │ │ PG │ - │ block│ │ block│ │ block│ │ block│ - │ │ │ │ │ │ │ │ - └─┬┬┬──┘ └─┬┬┬──┘ └─┬┬┬──┘ └─┬┬┬──┘ - │││G3P3S3 │││G2P2S2 │││G1P1S1 │││G0P0S0 - ┌─▼▼▼────────▼▼▼────────▼▼▼────────▼▼▼──┐ - │ Carry Lookahead logic │ - │ with sign extension │ - └┬────┬───────┬──────────┬──────────┬───┘ - │ │ │ │ │ - ▼ ▼ ▼ ▼ ▼ - Cout S3 S1 S0 S0 + ``` + ┼ ┼ ┼ ┼ + ┌───▼───▼───┐ ┌───▼───▼───┐ + ┌────┤ Propagate │ ┌────┤ Propagate │ + │SEL │ signals │ │SEL │ signals │ + ┌────▼─┐ └───────────┘ ┌────▼─┐ └───────────┘ + │ │ │ │ + ┌─┤2:1MUX│◄────────────────┬─┤2:1MUX│◄────────────────┬─Cin + │ │ │ │ │ │ │ + │ └────▲─┘ ┼ ┼ │ └────▲─┘ ┼ ┼ │ + ┌──▼───┐ │ ┌───▼───▼───┐ │ │ ┌───▼───▼───┐ │ + │ SIGN │ │ │ Adders │◄─┘ │ │ Adders │◄─┘ + │Extend│ └────┤ │ └────┤ │ + └──┬───┘ └─────┬─────┘ └─────┬─────┘ + │ │ │ + ▼ ▼ ▼ + Cout Sums Sums ``` Description of the __init__ method. diff --git a/ariths_gen/multi_bit_circuits/dividers/array_divider.py b/ariths_gen/multi_bit_circuits/dividers/array_divider.py index d3b13f9..0c9f71b 100644 --- a/ariths_gen/multi_bit_circuits/dividers/array_divider.py +++ b/ariths_gen/multi_bit_circuits/dividers/array_divider.py @@ -35,44 +35,56 @@ class ArrayDivider(ArithmeticCircuit): Design is based on series of iterative subtractions. ``` - 0 B2 0 B1 A2 B0 - │ │ │ │ │ │ - │ │ │ │ │ │ - ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ - │ │ │ │ │ │ - ┌─┤ FS │◄─┤ FS │◄─┤ FS │ - │ │ │ │ │ │ │ - │ └──────┘ └───┬──┘ └───┬──┘ - │ │ │0 │ │A2 - │ ┌─▼───▼┐ ┌─▼───▼┐ - ├────────────►│2:1MUX├─►│2:1MUX│ - │ └───┬──┘ └───┬──┘ A1 B0 - │ MX0│ B2 MX1│ B1 │ │ - │ │ │ │ │ │ │ - │ ┌─▼─▼──┐ ┌─▼─▼──┐ ┌─▼──▼─┐ - │ │ │ │ │ │ │ - │ ┌─┤ FS │◄─┤ FS │◄─┤ FS │ - │ │ │ │ │ │ │ │ - │ │ └──────┘ └───┬──┘ └───┬──┘ - │ │ │ │MX1 │ │A1 - │ │ ┌─▼───▼┐ ┌─▼───▼┐ - │ ├────────────►│2:1MUX├─►│2:1MUX│ - │ │ └───┬──┘ └───┬──┘ A0 B0 - │ │ MX2│ B2 MX3│ B1 │ │ - │ │ │ │ │ │ │ │ - │ │ ┌─▼─▼──┐ ┌─▼─▼──┐ ┌─▼──▼─┐ - │ │ │ │ │ │ │ │ - │ │ ┌─┤ FS │◄─┤ FS │◄─┤ FS │ - │ │ │ │ │ │ │ │ │ - │ │ │ └──────┘ └──────┘ └──────┘ - │ │ │ - ┌──▼──┐ ┌──▼──┐ ┌──▼──┐ - │ │ │ │ │ │ - │ NOT │ │ NOT │ │ NOT │ - │ │ │ │ │ │ - └──┬──┘ └──┬──┘ └──┬──┘ - ▼ ▼ ▼ - Q2 Q1 Q0 + 0 B3 0 B2 0 B1 A3 B0 + │ │ │ │ │ │ │ │ + │ │ │ │ │ │ │ │ + ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ ┌─▼──▼─┐ + │ │ │ │ │ │ │ │ + ┌─┤ FS │◄─┤ FS │◄─┤ FS │◄─┤ FS │◄─ 0 + │ │ │ │ │ │ │ │ │ + │ └──────┘ └───┬──┘ └───┬──┘ └───┬──┘ + │ │ │0 │ │0 │ │A3 + │ ┌─▼───▼┐ ┌─▼───▼┐ ┌─▼───▼┐ + ├────────────►│2:1MUX├─►│2:1MUX├─►│2:1MUX│ + │ └───┬──┘ └───┬──┘ └───┬──┘ + │ MX0│ B3 MX1│ B2 MX2│ B1 A2 B0 + │ │ │ │ │ │ │ │ │ + │ ┌─▼─▼──┐ ┌─▼─▼──┐ ┌─▼──▼─┐ ┌─▼──▼─┐ + │ │ │ │ │ │ │ │ │ + │ ┌─┤ FS │◄─┤ FS │◄─┤ FS │◄─┤ FS │◄─ 0 + │ │ │ │ │ │ │ │ │ │ + │ │ └──────┘ └───┬──┘ └───┬──┘ └───┬──┘ + │ │ │ │MX1 │ │MX2 │ │A2 + │ │ ┌─▼───▼┐ ┌─▼───▼┐ ┌─▼───▼┐ + │ ├────────────►│2:1MUX├─►│2:1MUX│─►│2:1MUX│ + │ │ └───┬──┘ └───┬──┘ └───┬──┘ + │ │ MX3│ B3 MX4│ B2 MX5│ B1 A1 B0 + │ │ │ │ │ │ │ │ │ │ + │ │ ┌─▼─▼──┐ ┌─▼─▼──┐ ┌─▼──▼─┐ ┌─▼──▼─┐ + │ │ │ │ │ │ │ │ │ │ + │ │ ┌─┤ FS │◄─┤ FS │◄─┤ FS │◄─┤ FS │◄─ 0 + │ │ │ │ │ │ │ │ │ │ │ + │ │ │ └──────┘ └───┬──┘ └───┬──┘ └───┬──┘ + │ │ │ │ │MX4 │ │MX5 │ │A1 + │ │ │ ┌─▼───▼┐ ┌─▼───▼┐ ┌─▼───▼┐ + │ │ │────────────►│2:1MUX├─►│2:1MUX│─►│2:1MUX│ + │ │ │ └───┬──┘ └───┬──┘ └───┬──┘ + │ │ │ MX6│ B3 MX7│ B2 MX8│ B1 A0 B0 + │ │ │ │ │ │ │ │ │ │ │ + │ │ │ ┌─▼─▼──┐ ┌─▼─▼──┐ ┌─▼──▼─┐ ┌─▼──▼─┐ + │ │ │ │ │ │ │ │ │ │ │ + │ │ │ ┌─┤ FS │◄─┤ FS │◄─┤ FS │◄─┤ FS │◄─ 0 + │ │ │ │ │ │ │ │ │ │ │ │ + │ │ │ │ └──────┘ └──────┘ └──────┘ └──────┘ + │ │ │ │ + │ │ │ │ + ┌──▼──┐ ┌──▼──┐ ┌──▼──┐ ┌──▼──┐ + │ │ │ │ │ │ │ │ + │ NOT │ │ NOT │ │ NOT │ │ NOT │ + │ │ │ │ │ │ │ │ + └──┬──┘ └──┬──┘ └──┬──┘ └──┬──┘ + ▼ ▼ ▼ ▼ + Q3 Q2 Q1 Q0 ``` Description of the __init__ method. diff --git a/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py index d23e4e6..67daa2a 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py @@ -33,6 +33,47 @@ class UnsignedArrayMultiplier(MultiplierCircuit): Downside is its rather big area because it is composed of many logic gates. + ``` + A3B0 A2B0 A1B0 A0B0 + │ │ │ │ │ │ │ │ + ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ + │AND│ │AND│ │AND│ │AND│ + └┬──┘ └┬──┘ └┬──┘ └─┬─┘ + A3B1 │ A2B1 │ A1B1 │ A0B1 │ + ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ + │AND│ │ │AND│ │ │AND│ │ │AND│ │ + └┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ + │ │ │ │ │ │ │ │ + ┌───▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ + │ │ │ │ │ │ │ │ │ + ┌───────┤ HA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ + │ │ │ │ │ │ │ │ │ │ + │ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ + │ A3B2 │ A2B2 │ A1B2 │ A0B2 │ │ + │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │ + │ │AND│ │ │AND│ │ │AND│ │ │AND│ │ │ + │ └┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │ + │ │ │ │ │ │ │ │ │ │ + ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ + │ │ │ │ │ │ │ │ │ │ + ┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ + │ │ │ │ │ │ │ │ │ │ │ + │ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ │ + │ A3B3 │ A2B3 │ A1B3 │ A0B3 │ │ │ + │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │ │ + │ │AND│ │ │AND│ │ │AND│ │ │AND│ │ │ │ + │ └┬──┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │ │ + │ │ │ │ │ │ │ │ │ │ │ + ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ │ + │ │ │ │ │ │ │ │ │ │ │ + ┌──────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ │ + │ │ │ │ │ │ │ │ │ │ │ │ + │ └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ │ │ │ + │ │ │ │ │ │ │ │ + ▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼ + P7 P6 P5 P4 P3 P2 P1 P0 + ``` + Description of the __init__ method. Args: @@ -104,6 +145,47 @@ class SignedArrayMultiplier(MultiplierCircuit): Downside is its rather big area because it is composed of many logic gates. + ``` + A3B0 A2B0 A1B0 A0B0 + │ │ │ │ │ │ │ │ + ┌▼─▼─┐ ┌▼─▼┐ ┌▼─▼┐ ┌▼─▼┐ + │NAND│ │AND│ │AND│ │AND│ + └┬───┘ └┬──┘ └┬──┘ └─┬─┘ + A3B1 │ A2B1 │ A1B1 │ A0B1 │ + ┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ + │NAND│ │ │AND│ │ │AND│ │ │AND│ │ + 1 └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ + │ │ │ │ │ │ │ │ │ + ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ + │ │ │ │ │ │ │ │ │ + ┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ + │ │ │ │ │ │ │ │ │ │ + │ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ + │ A3B2 │ A2B2 │ A1B2 │ A0B2 │ │ + │ ┌▼─▼─┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ ┌▼─▼┐ │ │ + │ │NAND│ │ │AND│ │ │AND│ │ │AND│ │ │ + │ └┬───┘ │ └┬──┘ │ └┬──┘ │ └┬──┘ │ │ + │ │ │ │ │ │ │ │ │ │ + ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ + │ │ │ │ │ │ │ │ │ │ + ┌───────┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ + │ │ │ │ │ │ │ │ │ │ │ + │ └┬───┘ └┬───┘ └┬───┘ └─┬──┘ │ │ + │ A3B3 │ A2B3 │ A1B3 │ A0B3 │ │ │ + │ ┌▼─▼┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ ┌▼─▼─┐ │ │ │ + │ │AND│ │ │NAND│ │ │NAND│ │ │NAND│ │ │ │ + 1 │ └┬──┘ │ └┬───┘ │ └┬───┘ │ └┬───┘ │ │ │ + │ │ │ │ │ │ │ │ │ │ │ │ + ┌─▼──┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ ┌▼──▼┐ │ │ │ + │ │ │ │ │ │ │ │ │ │ │ │ │ + │XOR │◄──┤ FA │◄──┤ FA │◄──┤ FA │◄──┤ HA │ │ │ │ + │ │ │ │ │ │ │ │ │ │ │ │ │ + └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ └─┬──┘ │ │ │ + │ │ │ │ │ │ │ │ + ▼ ▼ ▼ ▼ ▼ ▼ ▼ ▼ + P7 P6 P5 P4 P3 P2 P1 P0 + ``` + Description of the __init__ method. Args: diff --git a/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py b/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py index 0602747..f0c74db 100644 --- a/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py +++ b/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py @@ -7,11 +7,11 @@ class AndGate(TwoInputLogicGate): """Class representing two input AND gate. ``` - ┌──────┐ - ──►│ & │ - │ ├─► - ──►│ │ - └──────┘ + ┌──────┐ + ───►│ & │ + │ ├─► + ───►│ │ + └──────┘ ``` Description of the __init__ method. @@ -66,11 +66,11 @@ class NandGate(TwoInputInvertedLogicGate): """Class representing two input NAND gate. ``` - ┌──────┐ - ──►│ & │ - │ │O──► - ──►│ │ - └──────┘ + ┌──────┐ + ───►│ & │ + │ │O──► + ───►│ │ + └──────┘ ``` Description of the __init__ method. @@ -129,11 +129,11 @@ class OrGate(TwoInputLogicGate): """Class representing two input OR gate. ``` - ┌──────┐ - ──►│ ≥1 │ - │ ├─► - ──►│ │ - └──────┘ + ┌──────┐ + ───►│ ≥1 │ + │ ├─► + ───►│ │ + └──────┘ ``` Description of the __init__ method. @@ -188,11 +188,11 @@ class NorGate(TwoInputInvertedLogicGate): """Class representing two input NOR gate. ``` - ┌──────┐ - ──►│ ≥1 │ - │ │O──► - ──►│ │ - └──────┘ + ┌──────┐ + ───►│ ≥1 │ + │ │O──► + ───►│ │ + └──────┘ ``` Description of the __init__ method. @@ -251,11 +251,11 @@ class XorGate(TwoInputLogicGate): """Class representing two input XOR gate. ``` - ┌──────┐ - ──►│ =1 │ - │ ├─► - ──►│ │ - └──────┘ + ┌──────┐ + ───►│ =1 │ + │ ├─► + ───►│ │ + └──────┘ ``` Description of the __init__ method. @@ -314,11 +314,11 @@ class XnorGate(TwoInputInvertedLogicGate): """Class representing two input XNOR gate. ``` - ┌──────┐ - ──►│ =1 │ - │ │O──► - ──►│ │ - └──────┘ + ┌──────┐ + ───►│ =1 │ + │ │O──► + ───►│ │ + └──────┘ ``` Description of the __init__ method. @@ -378,11 +378,11 @@ class NotGate(OneInputLogicGate): """Class representing one input NOT gate. ``` - ┌──────┐ - │ 1 │ - ──►│ │O─► - │ │ - └──────┘ + ┌──────┐ + │ 1 │ + ───►│ │O─► + │ │ + └──────┘ ``` Description of the __init__ method.