diff --git a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
index 7df5de4..2207164 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
@@ -311,16 +311,19 @@ class TwoOneMultiplexer(ThreeInputOneBitCircuit):
         if not self.use_verilog_instance:
             return super().get_init_v_flat()
 
-        # TODO - replace by one verilog_instance_format!
-        neg_out_w_name = f"neg_{self.out.get_wire(0).name}"
-        return f"  wire {neg_out_w_name};\n  " + self.use_verilog_instance.format(
-            **{
-                "unit": self.prefix,
-                "wirea": f"1'b{self.a.value}" if self.a.is_const() else self.a.name,
-                "wireb": f"1'b{self.b.value}" if self.b.is_const() else self.b.name,
-                "wires": f"1'b{self.c.value}" if self.c.is_const() else self.c.name,
-                "wirey": neg_out_w_name,
-            }) + ";\n" + f"  assign {self.out.get_wire(0).name} = ~{neg_out_w_name};\n"
+        if self.out[0].is_const():
+            return ""
+        else:
+            # TODO - replace by one verilog_instance_format!
+            neg_out_w_name = f"neg_{self.out.get_wire(0).name}"
+            return f"  wire {neg_out_w_name};\n  " + self.use_verilog_instance.format(
+                **{
+                    "unit": self.prefix,
+                    "wirea": self.a.get_wire_value_v_hier(), # former version:  f"1'b{self.a.value}" if self.a.is_const() else self.a.name,
+                    "wireb": self.b.get_wire_value_v_hier(), #f"1'b{self.b.value}" if self.b.is_const() else self.b.name,
+                    "wires": self.c.get_wire_value_v_hier(), #f"1'b{self.c.value}" if self.c.is_const() else self.c.name,
+                    "wirey": neg_out_w_name,
+                }) + ";\n" + f"  assign {self.out.get_wire(0).name} = ~{neg_out_w_name};\n"
 
     def get_self_init_v_hier(self):
         """ support of custom PDK """
diff --git a/ariths_gen/wire_components/buses.py b/ariths_gen/wire_components/buses.py
index ed532bf..f7c91f5 100644
--- a/ariths_gen/wire_components/buses.py
+++ b/ariths_gen/wire_components/buses.py
@@ -75,11 +75,9 @@ class Bus():
         Returns:
             Wire: Returning wire from the bus.
         """
+        assert wire_index < self.N, f"Wire index {wire_index} is out of bounds of the bus {self.prefix} with size {self.N}"
         return self.bus[wire_index]
 
-    def __getitem__(self, i):
-        return self.bus[i]
-
     def __getitem__(self, i):
         return self.get_wire(i)