From 49bbc86a0fbb2539178bebc9c8b0590e037e4c00 Mon Sep 17 00:00:00 2001 From: Vojta Mrazek Date: Thu, 23 Mar 2023 13:39:32 +0100 Subject: [PATCH] accepts a wire as a bus --- ariths_gen/wire_components/wires.py | 5 +++++ tests/test_all.py | 17 +++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/ariths_gen/wire_components/wires.py b/ariths_gen/wire_components/wires.py index 019a4fa..8a68d1e 100644 --- a/ariths_gen/wire_components/wires.py +++ b/ariths_gen/wire_components/wires.py @@ -255,6 +255,11 @@ class Wire(): else: return f"" + """ define read-only parameter N""" + @property + def N(self): + return 1 + # Wires with constant values # class ConstantWireValue0(Wire): diff --git a/tests/test_all.py b/tests/test_all.py index 75a9f7a..c8cd777 100644 --- a/tests/test_all.py +++ b/tests/test_all.py @@ -341,3 +341,20 @@ def test_direct(): expected = np.array([[0, 3, 0, 3], [2, 3, 2, 3], [0, 3, 0, 3], [2, 3, 2, 3]]) np.testing.assert_equal(r, expected) print(r) + +def test_wire_as_bus(): + """ accept a wire as a bus """ + class test_circuit(GeneralCircuit): + def __init__(self, a: Wire, b: Wire, c: Bus, prefix="test_circuit", **kwargs): + super().__init__(prefix=prefix, name="test_circuit", inputs=[a, b, c], out_N=1, **kwargs) + g = self.add_component(AndGate(a, b, prefix="g2")) + g2 = self.add_component(AndGate(g.out, c[0], prefix="g2")) + g3 = self.add_component(AndGate(g2.out, c[1], prefix="g2")) + self.out[0] = g3.out + + circ = test_circuit(Wire("a"), Wire("b"), Bus("c", 2), "c1") + r = circ(np.array([0, 1]), + np.array([0, 1]).reshape(-1, 1), + np.arange(4).reshape(-1, 1, 1)) + assert r.sum() == 1 + assert r[-1, -1, -1] == 1 \ No newline at end of file