.model s_wallace_cska4 .inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3] .outputs s_wallace_cska4_out[0] s_wallace_cska4_out[1] s_wallace_cska4_out[2] s_wallace_cska4_out[3] s_wallace_cska4_out[4] s_wallace_cska4_out[5] s_wallace_cska4_out[6] s_wallace_cska4_out[7] .names vdd 1 .names gnd 0 .subckt and_gate a=a[2] b=b[0] out=s_wallace_cska4_and_2_0 .subckt and_gate a=a[1] b=b[1] out=s_wallace_cska4_and_1_1 .subckt ha a=s_wallace_cska4_and_2_0 b=s_wallace_cska4_and_1_1 ha_xor0=s_wallace_cska4_ha0_xor0 ha_and0=s_wallace_cska4_ha0_and0 .subckt nand_gate a=a[3] b=b[0] out=s_wallace_cska4_nand_3_0 .subckt and_gate a=a[2] b=b[1] out=s_wallace_cska4_and_2_1 .subckt fa a=s_wallace_cska4_ha0_and0 b=s_wallace_cska4_nand_3_0 cin=s_wallace_cska4_and_2_1 fa_xor1=s_wallace_cska4_fa0_xor1 fa_or0=s_wallace_cska4_fa0_or0 .subckt nand_gate a=a[3] b=b[1] out=s_wallace_cska4_nand_3_1 .subckt fa a=s_wallace_cska4_fa0_or0 b=vdd cin=s_wallace_cska4_nand_3_1 fa_xor1=s_wallace_cska4_fa1_xor1 fa_or0=s_wallace_cska4_fa1_or0 .subckt and_gate a=a[1] b=b[2] out=s_wallace_cska4_and_1_2 .subckt nand_gate a=a[0] b=b[3] out=s_wallace_cska4_nand_0_3 .subckt ha a=s_wallace_cska4_and_1_2 b=s_wallace_cska4_nand_0_3 ha_xor0=s_wallace_cska4_ha1_xor0 ha_and0=s_wallace_cska4_ha1_and0 .subckt and_gate a=a[2] b=b[2] out=s_wallace_cska4_and_2_2 .subckt nand_gate a=a[1] b=b[3] out=s_wallace_cska4_nand_1_3 .subckt fa a=s_wallace_cska4_ha1_and0 b=s_wallace_cska4_and_2_2 cin=s_wallace_cska4_nand_1_3 fa_xor1=s_wallace_cska4_fa2_xor1 fa_or0=s_wallace_cska4_fa2_or0 .subckt nand_gate a=a[3] b=b[2] out=s_wallace_cska4_nand_3_2 .subckt fa a=s_wallace_cska4_fa2_or0 b=s_wallace_cska4_fa1_or0 cin=s_wallace_cska4_nand_3_2 fa_xor1=s_wallace_cska4_fa3_xor1 fa_or0=s_wallace_cska4_fa3_or0 .subckt and_gate a=a[0] b=b[0] out=s_wallace_cska4_and_0_0 .subckt and_gate a=a[1] b=b[0] out=s_wallace_cska4_and_1_0 .subckt and_gate a=a[0] b=b[2] out=s_wallace_cska4_and_0_2 .subckt nand_gate a=a[2] b=b[3] out=s_wallace_cska4_nand_2_3 .subckt and_gate a=a[0] b=b[1] out=s_wallace_cska4_and_0_1 .subckt and_gate a=a[3] b=b[3] out=s_wallace_cska4_and_3_3 .names s_wallace_cska4_and_1_0 s_wallace_cska4_u_cska6_a[0] 1 1 .names s_wallace_cska4_and_0_2 s_wallace_cska4_u_cska6_a[1] 1 1 .names s_wallace_cska4_fa0_xor1 s_wallace_cska4_u_cska6_a[2] 1 1 .names s_wallace_cska4_fa1_xor1 s_wallace_cska4_u_cska6_a[3] 1 1 .names s_wallace_cska4_nand_2_3 s_wallace_cska4_u_cska6_a[4] 1 1 .names s_wallace_cska4_fa3_or0 s_wallace_cska4_u_cska6_a[5] 1 1 .names s_wallace_cska4_and_0_1 s_wallace_cska4_u_cska6_b[0] 1 1 .names s_wallace_cska4_ha0_xor0 s_wallace_cska4_u_cska6_b[1] 1 1 .names s_wallace_cska4_ha1_xor0 s_wallace_cska4_u_cska6_b[2] 1 1 .names s_wallace_cska4_fa2_xor1 s_wallace_cska4_u_cska6_b[3] 1 1 .names s_wallace_cska4_fa3_xor1 s_wallace_cska4_u_cska6_b[4] 1 1 .names s_wallace_cska4_and_3_3 s_wallace_cska4_u_cska6_b[5] 1 1 .subckt u_cska6 a[0]=s_wallace_cska4_u_cska6_a[0] a[1]=s_wallace_cska4_u_cska6_a[1] a[2]=s_wallace_cska4_u_cska6_a[2] a[3]=s_wallace_cska4_u_cska6_a[3] a[4]=s_wallace_cska4_u_cska6_a[4] a[5]=s_wallace_cska4_u_cska6_a[5] b[0]=s_wallace_cska4_u_cska6_b[0] b[1]=s_wallace_cska4_u_cska6_b[1] b[2]=s_wallace_cska4_u_cska6_b[2] b[3]=s_wallace_cska4_u_cska6_b[3] b[4]=s_wallace_cska4_u_cska6_b[4] b[5]=s_wallace_cska4_u_cska6_b[5] u_cska6_out[0]=s_wallace_cska4_u_cska6_ha0_xor0 u_cska6_out[1]=s_wallace_cska4_u_cska6_fa0_xor1 u_cska6_out[2]=s_wallace_cska4_u_cska6_fa1_xor1 u_cska6_out[3]=s_wallace_cska4_u_cska6_fa2_xor1 u_cska6_out[4]=s_wallace_cska4_u_cska6_fa3_xor1 u_cska6_out[5]=s_wallace_cska4_u_cska6_fa4_xor1 u_cska6_out[6]=s_wallace_cska4_u_cska6_mux2to11_xor0 .subckt not_gate a=s_wallace_cska4_u_cska6_mux2to11_xor0 out=s_wallace_cska4_xor0 .names s_wallace_cska4_and_0_0 s_wallace_cska4_out[0] 1 1 .names s_wallace_cska4_u_cska6_ha0_xor0 s_wallace_cska4_out[1] 1 1 .names s_wallace_cska4_u_cska6_fa0_xor1 s_wallace_cska4_out[2] 1 1 .names s_wallace_cska4_u_cska6_fa1_xor1 s_wallace_cska4_out[3] 1 1 .names s_wallace_cska4_u_cska6_fa2_xor1 s_wallace_cska4_out[4] 1 1 .names s_wallace_cska4_u_cska6_fa3_xor1 s_wallace_cska4_out[5] 1 1 .names s_wallace_cska4_u_cska6_fa4_xor1 s_wallace_cska4_out[6] 1 1 .names s_wallace_cska4_xor0 s_wallace_cska4_out[7] 1 1 .end .model u_cska6 .inputs a[0] a[1] a[2] a[3] a[4] a[5] b[0] b[1] b[2] b[3] b[4] b[5] .outputs u_cska6_out[0] u_cska6_out[1] u_cska6_out[2] u_cska6_out[3] u_cska6_out[4] u_cska6_out[5] u_cska6_out[6] .names vdd 1 .names gnd 0 .subckt xor_gate a=a[0] b=b[0] out=u_cska6_xor0 .subckt ha a=a[0] b=b[0] ha_xor0=u_cska6_ha0_xor0 ha_and0=u_cska6_ha0_and0 .subckt xor_gate a=a[1] b=b[1] out=u_cska6_xor1 .subckt fa a=a[1] b=b[1] cin=u_cska6_ha0_and0 fa_xor1=u_cska6_fa0_xor1 fa_or0=u_cska6_fa0_or0 .subckt xor_gate a=a[2] b=b[2] out=u_cska6_xor2 .subckt fa a=a[2] b=b[2] cin=u_cska6_fa0_or0 fa_xor1=u_cska6_fa1_xor1 fa_or0=u_cska6_fa1_or0 .subckt xor_gate a=a[3] b=b[3] out=u_cska6_xor3 .subckt fa a=a[3] b=b[3] cin=u_cska6_fa1_or0 fa_xor1=u_cska6_fa2_xor1 fa_or0=u_cska6_fa2_or0 .subckt and_gate a=u_cska6_xor0 b=u_cska6_xor2 out=u_cska6_and_propagate00 .subckt and_gate a=u_cska6_xor1 b=u_cska6_xor3 out=u_cska6_and_propagate01 .subckt and_gate a=u_cska6_and_propagate00 b=u_cska6_and_propagate01 out=u_cska6_and_propagate02 .subckt mux2to1 d0=u_cska6_fa2_or0 d1=gnd sel=u_cska6_and_propagate02 mux2to1_xor0=u_cska6_mux2to10_and1 .subckt xor_gate a=a[4] b=b[4] out=u_cska6_xor4 .subckt fa a=a[4] b=b[4] cin=u_cska6_mux2to10_and1 fa_xor1=u_cska6_fa3_xor1 fa_or0=u_cska6_fa3_or0 .subckt xor_gate a=a[5] b=b[5] out=u_cska6_xor5 .subckt fa a=a[5] b=b[5] cin=u_cska6_fa3_or0 fa_xor1=u_cska6_fa4_xor1 fa_or0=u_cska6_fa4_or0 .subckt and_gate a=u_cska6_xor4 b=u_cska6_xor5 out=u_cska6_and_propagate13 .subckt mux2to1 d0=u_cska6_fa4_or0 d1=u_cska6_mux2to10_and1 sel=u_cska6_and_propagate13 mux2to1_xor0=u_cska6_mux2to11_xor0 .names u_cska6_ha0_xor0 u_cska6_out[0] 1 1 .names u_cska6_fa0_xor1 u_cska6_out[1] 1 1 .names u_cska6_fa1_xor1 u_cska6_out[2] 1 1 .names u_cska6_fa2_xor1 u_cska6_out[3] 1 1 .names u_cska6_fa3_xor1 u_cska6_out[4] 1 1 .names u_cska6_fa4_xor1 u_cska6_out[5] 1 1 .names u_cska6_mux2to11_xor0 u_cska6_out[6] 1 1 .end .model mux2to1 .inputs d0 d1 sel .outputs mux2to1_xor0 .names vdd 1 .names gnd 0 .subckt and_gate a=d1 b=sel out=mux2to1_and0 .subckt not_gate a=sel out=mux2to1_not0 .subckt and_gate a=d0 b=mux2to1_not0 out=mux2to1_and1 .subckt xor_gate a=mux2to1_and0 b=mux2to1_and1 out=mux2to1_xor0 .end .model fa .inputs a b cin .outputs fa_xor1 fa_or0 .names vdd 1 .names gnd 0 .subckt xor_gate a=a b=b out=fa_xor0 .subckt and_gate a=a b=b out=fa_and0 .subckt xor_gate a=fa_xor0 b=cin out=fa_xor1 .subckt and_gate a=fa_xor0 b=cin out=fa_and1 .subckt or_gate a=fa_and0 b=fa_and1 out=fa_or0 .end .model ha .inputs a b .outputs ha_xor0 ha_and0 .names vdd 1 .names gnd 0 .subckt xor_gate a=a b=b out=ha_xor0 .subckt and_gate a=a b=b out=ha_and0 .end .model not_gate .inputs a .outputs out .names vdd 1 .names gnd 0 .names a out 0 1 .end .model or_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 1- 1 -1 1 .end .model nand_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 0- 1 -0 1 .end .model xor_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 01 1 10 1 .end .model and_gate .inputs a b .outputs out .names vdd 1 .names gnd 0 .names a b out 11 1 .end