.model u_cska4
.inputs a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3]
.outputs u_cska4_out[0] u_cska4_out[1] u_cska4_out[2] u_cska4_out[3] u_cska4_out[4]
.names vdd
1
.names gnd
0
.names a[0] b[0] u_cska4_xor0
01 1
10 1
.names a[0] b[0] u_cska4_ha0_xor0
01 1
10 1
.names a[0] b[0] u_cska4_ha0_and0
11 1
.names a[1] b[1] u_cska4_xor1
01 1
10 1
.names a[1] b[1] u_cska4_fa0_xor0
01 1
10 1
.names a[1] b[1] u_cska4_fa0_and0
11 1
.names u_cska4_fa0_xor0 u_cska4_ha0_and0 u_cska4_fa0_xor1
01 1
10 1
.names u_cska4_fa0_xor0 u_cska4_ha0_and0 u_cska4_fa0_and1
11 1
.names u_cska4_fa0_and0 u_cska4_fa0_and1 u_cska4_fa0_or0
1- 1
-1 1
.names a[2] b[2] u_cska4_xor2
01 1
10 1
.names a[2] b[2] u_cska4_fa1_xor0
01 1
10 1
.names a[2] b[2] u_cska4_fa1_and0
11 1
.names u_cska4_fa1_xor0 u_cska4_fa0_or0 u_cska4_fa1_xor1
01 1
10 1
.names u_cska4_fa1_xor0 u_cska4_fa0_or0 u_cska4_fa1_and1
11 1
.names u_cska4_fa1_and0 u_cska4_fa1_and1 u_cska4_fa1_or0
1- 1
-1 1
.names a[3] b[3] u_cska4_xor3
01 1
10 1
.names a[3] b[3] u_cska4_fa2_xor0
01 1
10 1
.names a[3] b[3] u_cska4_fa2_and0
11 1
.names u_cska4_fa2_xor0 u_cska4_fa1_or0 u_cska4_fa2_xor1
01 1
10 1
.names u_cska4_fa2_xor0 u_cska4_fa1_or0 u_cska4_fa2_and1
11 1
.names u_cska4_fa2_and0 u_cska4_fa2_and1 u_cska4_fa2_or0
1- 1
-1 1
.names u_cska4_xor0 u_cska4_xor2 u_cska4_and_propagate00
11 1
.names u_cska4_xor1 u_cska4_xor3 u_cska4_and_propagate01
11 1
.names u_cska4_and_propagate00 u_cska4_and_propagate01 u_cska4_and_propagate02
11 1
.names u_cska4_and_propagate02 u_cska4_mux2to10_not0
0 1
.names u_cska4_fa2_or0 u_cska4_mux2to10_not0 u_cska4_mux2to10_and1
11 1
.names u_cska4_ha0_xor0 u_cska4_out[0]
1 1
.names u_cska4_fa0_xor1 u_cska4_out[1]
1 1
.names u_cska4_fa1_xor1 u_cska4_out[2]
1 1
.names u_cska4_fa2_xor1 u_cska4_out[3]
1 1
.names u_cska4_mux2to10_and1 u_cska4_out[4]
1 1
.end