diff --git a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py
index 59174d6..c2825d4 100644
--- a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py
@@ -9,7 +9,7 @@ from ariths_gen.core.logic_gate_circuits import (
     MultipleInputLogicGate
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
-    PGLogicBlock
+    partialAdder
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
@@ -81,13 +81,13 @@ class UnsignedCarryLookaheadAdder(GeneralCircuit):
 
             # Gradual addition of propagate/generate logic blocks and AND/OR gates for Cout bits generation, XOR gates for Sum bits generation
             for i in range(block_size):
-                pg_block = PGLogicBlock(self.a.get_wire((block_n*cla_block_size)+i), self.b.get_wire((block_n*cla_block_size)+i), prefix=self.prefix+"_pg_logic"+str(self.get_instance_num(cls=PGLogicBlock)))
+                pg_block = partialAdder(self.a.get_wire((block_n*cla_block_size)+i), self.b.get_wire((block_n*cla_block_size)+i), cin, prefix=self.prefix+"_partialAdder"+str(self.get_instance_num(cls=partialAdder)))
+                
                 propagate_sig.append(pg_block.get_propagate_wire())
                 generate_sig.append(pg_block.get_generate_wire())
-                self.add_component(pg_block)
 
-                self.add_component(XorGateComponent(pg_block.get_sum_wire(), cin, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
-                self.out.connect(i+(block_n*cla_block_size), self.get_previous_component().out.get_wire(0))
+                self.add_component(pg_block)
+                self.out.connect(i+(block_n*cla_block_size), pg_block.get_sum_wire())
 
                 # List of AND gates outputs that are later combined in a multi-bit OR gate
                 composite_or_gates_inputs = []
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/__init__.py b/ariths_gen/one_bit_circuits/one_bit_components/__init__.py
index 911a919..35ec37c 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/__init__.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/__init__.py
@@ -3,7 +3,7 @@ from .two_input_one_bit_components import (
     HalfSubtractor,
     XorGateComponent,
     XnorGateComponent,
-    PGLogicBlock
+    partialAdder
 )
 
 from .three_input_one_bit_components import (
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
index e969879..b43242e 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
@@ -177,15 +177,15 @@ class HalfAdder(TwoInputOneBitCircuit):
                f"endmodule"
 
 
-class PGLogicBlock(TwoInputOneBitCircuit):
+class partialAdder(TwoInputOneBitCircuit):
     """Class representing two input one bit propagate/generate logic block.
 
     ```
-        ┌──────┐
-    ───►│      ├─► P
-        │      ├─► G
-    ───►│      ├─► S
-        └──────┘
+            ┌──────┐
+    A   ───►│      ├─► P
+    B   ───►│      ├─► G
+    Cin ───►│      ├─► S
+            └──────┘
     ```
 
     Description of the __init__ method.
@@ -196,7 +196,7 @@ class PGLogicBlock(TwoInputOneBitCircuit):
         prefix (str, optional): Prefix name of pg logic block. Defaults to "".
         name (str, optional): Name of pg logic block. Defaults to "pg_logic".
     """
-    def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), prefix: str = "", name: str = "pg_logic"):
+    def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), cin: Wire = Wire(name="cin"), prefix: str = "", name: str = "pg_logic"):
         super().__init__(a, b, prefix=prefix, name=name)
         # 3 wires for component's bus output (propagate, generate, sum)
         self.out = Bus(self.prefix+"_out", 3)
@@ -208,12 +208,12 @@ class PGLogicBlock(TwoInputOneBitCircuit):
         generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
         self.add_component(generate_and)
 
-        sum_xor = Maji(propagate_or.out, generate_and.out, ConstantWireValue0(), [False, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)        
-        self.add_component(sum_xor)
+        fa = FullAdder(self, a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)), parent_component=self)
+        self.add_component(fa)
 
         self.out.connect(0, propagate_or.out)
         self.out.connect(1, generate_and.out)
-        self.out.connect(2, sum_xor.out)
+        self.out.connect(2, fa.get_sum_wire())
 
     def get_propagate_wire(self):
         """Get output wire carrying propagate signal value.
diff --git a/generate_test.py b/generate_test.py
index f040f9f..53c9dd4 100644
--- a/generate_test.py
+++ b/generate_test.py
@@ -18,7 +18,7 @@ from ariths_gen.one_bit_circuits.one_bit_components import (
     FullAdder,
     XorGateComponent,
     XnorGateComponent,
-    PGLogicBlock,
+    partialAdder,
     FullAdderPG,
     TwoOneMultiplexer,
     HalfSubtractor,