From c61244c9660c118843e284dce679ad843f344707 Mon Sep 17 00:00:00 2001
From: Lukas Plevac <iplevac@fit.vutbr.cz>
Date: Tue, 8 Oct 2024 14:28:38 +0200
Subject: [PATCH] Fixed RCA by test

---
 .../three_input_one_bit_components.py         |  4 +-
 tests/test_maji_adder.py                      | 40 +++++++++++++++++++
 2 files changed, 42 insertions(+), 2 deletions(-)
 create mode 100644 tests/test_maji_adder.py

diff --git a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
index 6c9de35..438fcbf 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
@@ -36,9 +36,9 @@ class FullAdder(ThreeInputOneBitCircuit):
         self.add_component(obj_maji1)
         
         # cout
-        obj_maji2 = Maji(c, a, b [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=1, parent_component=self)
+        obj_maji2 = Maji(c, a, b, [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=1, parent_component=self)
         self.add_component(obj_maji2)
-        self.out.connect(1, obj_maji2)
+        self.out.connect(1, obj_maji2.out)
 
         # sum
         obj_maji3 = Maji(c, obj_maji1.out, obj_maji2.out, [False, False, True], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=0, parent_component=self)
diff --git a/tests/test_maji_adder.py b/tests/test_maji_adder.py
new file mode 100644
index 0000000..5c62b80
--- /dev/null
+++ b/tests/test_maji_adder.py
@@ -0,0 +1,40 @@
+
+from io import StringIO
+import os, sys
+
+DIR_PATH = os.path.dirname(os.path.abspath(__file__))
+sys.path.insert(0, os.path.join(DIR_PATH, '..'))
+
+from ariths_gen.core.arithmetic_circuits import GeneralCircuit
+from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
+from ariths_gen.wire_components import Bus
+
+from ariths_gen.pdk import *
+import os
+
+class MultiMaji(GeneralCircuit):
+    def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "maji", **kwargs):
+        super().__init__(prefix=prefix, name=name, out_N=a.N, inputs=[a, b], **kwargs)
+
+        self.out = Bus("out", a.N)
+
+        assert a.N == b.N
+
+        self.add = self.add_component(UnsignedRippleCarryAdder(a, b, prefix=self.prefix, name=f"u_rca{a.N}", inner_component=False))
+        self.out.connect_bus(connecting_bus=self.add.out)
+
+# usage
+if __name__ == "__main__":
+    maji = MultiMaji(Bus("a", 8), Bus("b", 8))
+
+    # try to test maji
+    for a in range(256):
+        for b in range(256):
+            testOut     = maji(a, b)
+            expectedBus = (a + b) & 0xFF
+
+        if (expectedBus != testOut):
+            print(f"expexted {expectedBus} have {testOut}")
+            exit(1)
+        
+    print("Test maji as Ripple Carry Adder OK")