From 9e186d10edab510bffc15cefa955723bafdbff23 Mon Sep 17 00:00:00 2001 From: Honza Date: Fri, 18 Feb 2022 17:24:09 +0100 Subject: [PATCH] Typos fix and code cleanup. --- README.md | 8 ++++---- .../arithmetic_circuits/general_circuit.py | 2 +- .../adders/carry_lookahead_adder.py | 1 - .../adders/carry_skip_adder.py | 1 - .../adders/pg_ripple_carry_adder.py | 1 - .../adders/ripple_carry_adder.py | 1 - .../broken_array_multiplier.py | 1 - .../truncated_multiplier.py | 1 - .../multipliers/array_multiplier.py | 1 - .../multipliers/dadda_multiplier.py | 1 - .../multipliers/wallace_csa_multiplier.py | 1 - .../multipliers/wallace_multiplier.py | 1 - tests/test_all.py | 18 ++---------------- tests/test_cgp.py | 5 ++--- 14 files changed, 9 insertions(+), 34 deletions(-) diff --git a/README.md b/README.md index 3e8ece1..067f629 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ In contrast to standard HDL languages Python supports * Support of various PDKs (for using library cells as half-adders and full-adders) ## Prebuild circuits -To enable the fast work with the circuits, we published pre-build arithmetic circuits in various formats in [generated_circuits](generated_circuits) folder and as a [Release](https://github.com/ehw-fit/ariths-gen/releases). +To enable fast work with the circuits, we published pre-build arithmetic circuits in various formats in [generated_circuits](generated_circuits) folder and as a [Release](https://github.com/ehw-fit/ariths-gen/releases). ### Usage ```bash @@ -35,7 +35,7 @@ u_dadda.get_v_code_hier(open("h_u_dadda_cla8.v", "w")) See [Ripple Carry Adder](ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py) file for a basic example. ### Complex circuits -It is possible to combine some basic circuit to generate more complex circuits (such as MAC). The design can be parametrised (i.e., you can pass `UnsignedArraymultiplier` as an input parameter). +It is possible to combine some basic circuits to generate more complex circuits (such as MAC). The design can be parametrised (i.e., you can pass `UnsignedArraymultiplier` as an input parameter). ```py from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit @@ -87,7 +87,7 @@ python3 generate_axmuls.py ``` to get the approximate circuits. -The module supports also evaluation of the proposed circuits. You can call the instation as a function (even with numpy-array input) to obtain the results for one multiplication +The module also supports evaluation of the proposed circuits. You can call the instation as a function (even with numpy-array input) to obtain the results of multiplication operation ```py from ariths_gen.wire_components.buses import Bus @@ -101,7 +101,7 @@ bam = UnsignedBrokenArrayMultiplier(a, b, horizontal_cut=4, vertical_cut=4) print("43 * 84 = ", bam(43, 84), " expected: ", 43 * 84) # 43 * 84 = 3440 expected: 3612 ``` -even for all possible combinations +for all of the possible combinations. ```py # Evaluate all using b'casting diff --git a/ariths_gen/core/arithmetic_circuits/general_circuit.py b/ariths_gen/core/arithmetic_circuits/general_circuit.py index a6d7d73..42b90b3 100644 --- a/ariths_gen/core/arithmetic_circuits/general_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/general_circuit.py @@ -31,8 +31,8 @@ class GeneralCircuit(): self.components = [] self.circuit_wires = [] self.circuit_gates = [] - self.c_data_type = "uint64_t" self.signed = signed + self.c_data_type = "int64_t" if self.signed is True else "uint64_t" self.pyc = None # Python compiled function def __call__(self, *args): diff --git a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py index 20356a1..7599fe8 100644 --- a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py +++ b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py @@ -185,7 +185,6 @@ class SignedCarryLookaheadAdder(UnsignedCarryLookaheadAdder, ArithmeticCircuit): """ def __init__(self, a: Bus, b: Bus, cla_block_size: int = 4, prefix: str = "", name: str = "s_cla", **kwargs): super().__init__(a=a, b=b, cla_block_size=cla_block_size, prefix=prefix, name=name, signed=True, **kwargs) - self.c_data_type = "int64_t" # Additional XOR gates to ensure correct sign extension in case of sign addition sign_xor_1 = XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self) diff --git a/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py index 7ec7a86..7b75124 100644 --- a/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py +++ b/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py @@ -168,7 +168,6 @@ class SignedCarrySkipAdder(UnsignedCarrySkipAdder, ArithmeticCircuit): """ def __init__(self, a: Bus, b: Bus, bypass_block_size: int = 4, prefix: str = "", name: str = "s_cska", **kwargs): super().__init__(a=a, b=b, bypass_block_size=bypass_block_size, prefix=prefix, name=name, signed=True, **kwargs) - self.c_data_type = "int64_t" # Additional XOR gates to ensure correct sign extension in case of sign addition sign_xor_1 = XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self) diff --git a/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py b/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py index a19f6b8..2ee120e 100644 --- a/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py +++ b/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py @@ -131,7 +131,6 @@ class SignedPGRippleCarryAdder(UnsignedPGRippleCarryAdder, ArithmeticCircuit): """ def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_pg_rca", **kwargs): super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs) - self.c_data_type = "int64_t" # Additional XOR gates to ensure correct sign extension in case of sign addition sign_xor_1 = XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self) diff --git a/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py b/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py index 229e614..b75c7c0 100644 --- a/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py +++ b/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py @@ -107,7 +107,6 @@ class SignedRippleCarryAdder(UnsignedRippleCarryAdder, ArithmeticCircuit): """ def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_rca", **kwargs): super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs) - self.c_data_type = "int64_t" # Additional XOR gates to ensure correct sign extension in case of sign addition sign_xor_1 = XorGate(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self) diff --git a/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_array_multiplier.py b/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_array_multiplier.py index 087704f..fdf1d58 100644 --- a/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_array_multiplier.py +++ b/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_array_multiplier.py @@ -248,7 +248,6 @@ class SignedBrokenArrayMultiplier(MultiplierCircuit): assert vertical_cut >= horizontal_cut super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs) - self.c_data_type = "int64_t" # Bus sign extension in case buses have different lengths self.a.bus_extend(N=self.N, prefix=a.prefix) diff --git a/ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_multiplier.py b/ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_multiplier.py index 293f4d7..3463814 100644 --- a/ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_multiplier.py +++ b/ariths_gen/multi_bit_circuits/approximate_multipliers/truncated_multiplier.py @@ -210,7 +210,6 @@ class SignedTruncatedMultiplier(MultiplierCircuit): assert truncation_cut < self.N super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs) - self.c_data_type = "int64_t" # Bus sign extension in case buses have different lengths self.a.bus_extend(N=self.N, prefix=a.prefix) diff --git a/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py index 4817d92..10963e3 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py @@ -192,7 +192,6 @@ class SignedArrayMultiplier(MultiplierCircuit): def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_arrmul", **kwargs): self.N = max(a.N, b.N) super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs) - self.c_data_type = "int64_t" # Bus sign extension in case buses have different lengths self.a.bus_extend(N=self.N, prefix=a.prefix) diff --git a/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py index 7acfb1d..b908a08 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py @@ -156,7 +156,6 @@ class SignedDaddaMultiplier(MultiplierCircuit): def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_dadda_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs): self.N = max(a.N, b.N) super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs) - self.c_data_type = "int64_t" # Bus sign extension in case buses have different lengths self.a.bus_extend(N=self.N, prefix=a.prefix) diff --git a/ariths_gen/multi_bit_circuits/multipliers/wallace_csa_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/wallace_csa_multiplier.py index 64c1933..9202242 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/wallace_csa_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/wallace_csa_multiplier.py @@ -159,7 +159,6 @@ class SignedWallaceCSAMultiplier(MultiplierCircuit): def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallaceCSA_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs): self.N = max(a.N, b.N) super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs) - self.c_data_type = "int64_t" # Bus sign extension in case buses have different lengths self.a.bus_extend(N=self.N, prefix=a.prefix) diff --git a/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py index 868dd77..1d363ed 100644 --- a/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py +++ b/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py @@ -149,7 +149,6 @@ class SignedWallaceMultiplier(MultiplierCircuit): def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "s_wallace_cla", unsigned_adder_class_name: str = UnsignedCarryLookaheadAdder, **kwargs): self.N = max(a.N, b.N) super().__init__(a=a, b=b, prefix=prefix, name=name, out_N=self.N*2, signed=True, **kwargs) - self.c_data_type = "int64_t" # Bus sign extension in case buses have different lengths self.a.bus_extend(N=self.N, prefix=a.prefix) diff --git a/tests/test_all.py b/tests/test_all.py index 3e7fd19..30ebb24 100644 --- a/tests/test_all.py +++ b/tests/test_all.py @@ -1,4 +1,3 @@ - from ariths_gen.wire_components import ( Wire, ConstantWireValue0, @@ -28,14 +27,12 @@ from ariths_gen.multi_bit_circuits.multipliers import ( SignedWallaceMultiplier, ) - from ariths_gen.multi_bit_circuits.approximate_multipliers import ( UnsignedTruncatedMultiplier, SignedTruncatedMultiplier, UnsignedBrokenArrayMultiplier, SignedBrokenArrayMultiplier ) - import numpy as np @@ -76,7 +73,6 @@ def test_unsigned_approxmul(values = False): if values is True: np.testing.assert_array_equal(expected, r) - def test_unsigned_mul(): """ Test unsigned multipliers """ N = 7 @@ -86,14 +82,12 @@ def test_unsigned_mul(): bv = av.reshape(-1, 1) expected = av * bv - for c in [ UnsignedDaddaMultiplier, UnsignedArrayMultiplier, UnsignedWallaceMultiplier]: + for c in [UnsignedDaddaMultiplier, UnsignedArrayMultiplier, UnsignedWallaceMultiplier]: mul = c(a, b) assert mul(0, 0) == 0 r = mul(av, bv) np.testing.assert_array_equal(expected, r) - - def test_signed_mul(): """ Test signed multipliers """ N = 7 @@ -103,16 +97,12 @@ def test_signed_mul(): bv = av.reshape(-1, 1) expected = av * bv - for c in [ SignedDaddaMultiplier, SignedArrayMultiplier, SignedWallaceMultiplier]: + for c in [SignedDaddaMultiplier, SignedArrayMultiplier, SignedWallaceMultiplier]: mul = c(a, b) r = mul(av, bv) assert mul(0, 0) == 0 - - # r[r >= 2**(2*N-1)] -= 2**(2*N) # hack!!! two's complement not implemented yet np.testing.assert_array_equal(expected, r) - - def test_unsigned_add(): """ Test unsigned adders """ N = 7 @@ -127,8 +117,6 @@ def test_unsigned_add(): r = mul(av, bv) np.testing.assert_array_equal(expected, r) - - def test_signed_add(): """ Test signed adders """ N = 7 @@ -141,10 +129,8 @@ def test_signed_add(): for c in [SignedCarryLookaheadAdder, SignedPGRippleCarryAdder, SignedRippleCarryAdder, SignedCarrySkipAdder]: mul = c(a, b) r = mul(av, bv) - # r[r >= 2**(N)] -= 2**(N+1) # hack!!! two's complement not implemented yet np.testing.assert_array_equal(expected, r) - def test_mac(): class MAC(GeneralCircuit): def __init__(self, a: Bus, b: Bus, r: Bus, prefix: str = "", name: str = "mac", **kwargs): diff --git a/tests/test_cgp.py b/tests/test_cgp.py index 2df5511..5c9abf1 100644 --- a/tests/test_cgp.py +++ b/tests/test_cgp.py @@ -94,7 +94,6 @@ def test_cgp_signed_add(): assert add(0, 0) == 0 assert add2(0, 0) == 0 - # r[r >= 2**(N)] -= 2**(N+1) # hack!!! two's complement not implemented yet np.testing.assert_array_equal(expected, r) @@ -107,7 +106,7 @@ def test_unsigned_mul(): bv = av.reshape(-1, 1) expected = av * bv - for c in [ UnsignedDaddaMultiplier, UnsignedArrayMultiplier, UnsignedWallaceMultiplier]: + for c in [UnsignedDaddaMultiplier, UnsignedArrayMultiplier, UnsignedWallaceMultiplier]: mul = c(a, b) code = StringIO() mul.get_cgp_code_flat(code) @@ -127,7 +126,7 @@ def test_signed_mul(): bv = av.reshape(-1, 1) expected = av * bv - for c in [ SignedDaddaMultiplier, SignedArrayMultiplier, SignedWallaceMultiplier]: + for c in [SignedDaddaMultiplier, SignedArrayMultiplier, SignedWallaceMultiplier]: mul = c(a, b) code = StringIO() mul.get_cgp_code_flat(code)