From 995107eecc093c59f4c3a7ed6f34c7066ecc37b8 Mon Sep 17 00:00:00 2001 From: Vojta Mrazek Date: Thu, 23 Sep 2021 08:50:18 +0200 Subject: [PATCH] Removing of file closing --- ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py | 7 ------- ariths_gen/core/arithmetic_circuits/general_circuit.py | 7 ------- ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py | 4 ---- .../core/one_bit_circuits/two_input_one_bit_circuit.py | 2 -- 4 files changed, 20 deletions(-) diff --git a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py index 1e76475..e4003b8 100644 --- a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py @@ -295,7 +295,6 @@ class ArithmeticCircuit(): file_object.write(self.get_init_c_flat()+"\n") file_object.write(self.get_function_out_c_flat()) file_object.write(f" return {self.out.prefix}"+";\n}") - file_object.close() # HIERARCHICAL C # def get_function_blocks_c(self): @@ -399,7 +398,6 @@ class ArithmeticCircuit(): file_object.write(self.get_includes_c()) file_object.write(self.get_function_blocks_c()) file_object.write(self.get_circuit_c()) - file_object.close() """ VERILOG CODE GENERATION """ # FLAT VERILOG # @@ -448,7 +446,6 @@ class ArithmeticCircuit(): file_object.write(self.get_init_v_flat() + "\n") file_object.write(self.get_function_out_v_flat()) file_object.write(f"endmodule") - file_object.close() # HIERARCHICAL VERILOG # def get_function_blocks_v(self): @@ -556,7 +553,6 @@ class ArithmeticCircuit(): """ file_object.write(self.get_function_blocks_v()) file_object.write(self.get_circuit_v()) - file_object.close() """ BLIF CODE GENERATION """ # FLAT BLIF # @@ -614,7 +610,6 @@ class ArithmeticCircuit(): file_object.write(self.get_function_blif_flat()) file_object.write(self.get_function_out_blif()) file_object.write(f".end\n") - file_object.close() # HIERARCHICAL BLIF # def get_invocations_blif_hier(self): @@ -689,7 +684,6 @@ class ArithmeticCircuit(): """ file_object.write(self.get_circuit_blif()+"\n") file_object.write(self.get_function_blocks_blif()) - file_object.close() """ CGP CODE GENERATION """ # FLAT CGP # @@ -741,4 +735,3 @@ class ArithmeticCircuit(): file_object.write(self.get_parameters_cgp()) file_object.write(self.get_triplets_cgp()) file_object.write(self.get_outputs_cgp()) - file_object.close() diff --git a/ariths_gen/core/arithmetic_circuits/general_circuit.py b/ariths_gen/core/arithmetic_circuits/general_circuit.py index e92bf17..1caf514 100644 --- a/ariths_gen/core/arithmetic_circuits/general_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/general_circuit.py @@ -282,7 +282,6 @@ class GeneralCircuit(): file_object.write(self.get_init_c_flat()+"\n") file_object.write(self.get_function_out_c_flat()) file_object.write(f" return {self.out.prefix}"+";\n}") - file_object.close() # HIERARCHICAL C # def get_function_blocks_c(self): @@ -386,7 +385,6 @@ class GeneralCircuit(): file_object.write(self.get_includes_c()) file_object.write(self.get_function_blocks_c()) file_object.write(self.get_circuit_c()) - file_object.close() """ VERILOG CODE GENERATION """ # FLAT VERILOG # @@ -435,7 +433,6 @@ class GeneralCircuit(): file_object.write(self.get_init_v_flat() + "\n") file_object.write(self.get_function_out_v_flat()) file_object.write(f"endmodule") - file_object.close() # HIERARCHICAL VERILOG # def get_function_blocks_v(self): @@ -543,7 +540,6 @@ class GeneralCircuit(): """ file_object.write(self.get_function_blocks_v()) file_object.write(self.get_circuit_v()) - file_object.close() """ BLIF CODE GENERATION """ # FLAT BLIF # @@ -601,7 +597,6 @@ class GeneralCircuit(): file_object.write(self.get_function_blif_flat()) file_object.write(self.get_function_out_blif()) file_object.write(f".end\n") - file_object.close() # HIERARCHICAL BLIF # def get_invocations_blif_hier(self): @@ -678,7 +673,6 @@ class GeneralCircuit(): """ file_object.write(self.get_circuit_blif()+"\n") file_object.write(self.get_function_blocks_blif()) - file_object.close() """ CGP CODE GENERATION """ # FLAT CGP # @@ -730,4 +724,3 @@ class GeneralCircuit(): file_object.write(self.get_parameters_cgp()) file_object.write(self.get_triplets_cgp()) file_object.write(self.get_outputs_cgp()) - file_object.close() diff --git a/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py b/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py index 5c847e7..08d8be0 100644 --- a/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py +++ b/ariths_gen/core/logic_gate_circuits/logic_gate_circuit.py @@ -149,7 +149,6 @@ class TwoInputLogicGate(): file_object.write(self.get_includes_c()) file_object.write(self.get_prototype_c_flat()) file_object.write(" return "+(self.get_function_c())+";\n}") - file_object.close() # HIERARCHICAL C # def get_prototype_c_hier(self): @@ -260,7 +259,6 @@ class TwoInputLogicGate(): file_object.write(self.get_prototype_v_flat()) file_object.write(self.get_output_v_flat()) file_object.write(f"endmodule") - file_object.close() # HIERARCHICAL VERILOG # def get_prototype_v_hier(self): @@ -363,7 +361,6 @@ class TwoInputLogicGate(): file_object.write(self.get_declaration_blif()) file_object.write(self.get_function_blif_flat(top_modul=True)) file_object.write(f".end\n") - file_object.close() # HIERARCHICAL BLIF # def get_prototype_blif_hier(self): @@ -481,7 +478,6 @@ class TwoInputLogicGate(): """ file_object.write(self.get_parameters_cgp()) file_object.write(self.get_gate_triplet_cgp()) - file_object.close() class TwoInputInvertedLogicGate(TwoInputLogicGate): diff --git a/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py b/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py index b13106d..c630058 100644 --- a/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py +++ b/ariths_gen/core/one_bit_circuits/two_input_one_bit_circuit.py @@ -156,7 +156,6 @@ class TwoInputOneBitCircuit(ArithmeticCircuit): file_object.write(self.get_declarations_v_flat()) file_object.write(self.get_self_init_v_flat()) file_object.write(f"endmodule") - file_object.close() # HIERARCHICAL VERILOG # # Subcomponent generation @@ -292,7 +291,6 @@ class TwoInputOneBitCircuit(ArithmeticCircuit): file_object.write(self.get_declaration_blif()) file_object.write(self.get_function_blif_flat(top_modul=True)) file_object.write(f".end\n") - file_object.close() # HIERARCHICAL BLIF # # Subcomponent/self circuit generation