From 3c47407f80fb49474fad9e6b928442aaa5fb80df Mon Sep 17 00:00:00 2001 From: Vojta Mrazek Date: Mon, 7 Feb 2022 11:29:12 +0100 Subject: [PATCH] output rename --- .../core/arithmetic_circuits/arithmetic_circuit.py | 4 ++-- .../core/arithmetic_circuits/general_circuit.py | 6 ++++-- ariths_gen/multi_bit_circuits/cgp_circuit.py | 13 +++++++++++-- generate_mac.py | 2 +- tests/test_circuits_verilog.sh | 3 --- 5 files changed, 18 insertions(+), 10 deletions(-) diff --git a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py index 04a63f2..ef905db 100644 --- a/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/arithmetic_circuit.py @@ -17,8 +17,8 @@ class ArithmeticCircuit(GeneralCircuit): that are later used for generation into various representations. """ - def __init__(self, a, b, prefix: str, name: str, out_N: int, inner_component: bool = False, one_bit_circuit: bool = False, signed: bool = False): - super().__init__(prefix, name, out_N, inner_component, inputs=[a, b], signed=signed) + def __init__(self, a, b, prefix: str, name: str, out_N: int, inner_component: bool = False, one_bit_circuit: bool = False, signed: bool = False, **kwargs): + super().__init__(prefix, name, out_N, inner_component, inputs=[a, b], signed=signed, **kwargs) if one_bit_circuit is False: if prefix == "": self.prefix = name diff --git a/ariths_gen/core/arithmetic_circuits/general_circuit.py b/ariths_gen/core/arithmetic_circuits/general_circuit.py index 213cd69..047ed7d 100644 --- a/ariths_gen/core/arithmetic_circuits/general_circuit.py +++ b/ariths_gen/core/arithmetic_circuits/general_circuit.py @@ -16,14 +16,16 @@ class GeneralCircuit(): that are later used for generation into various representations. """ - def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list=[], signed: bool = False): + def __init__(self, prefix: str, name: str, out_N: int, inner_component: bool = False, inputs: list=[], signed: bool = False, outname = None): if prefix == "": self.prefix = name else: self.prefix = prefix + "_" + name self.inner_component = inner_component self.inputs = inputs - self.out = Bus(self.prefix+"_out", out_N, out_bus=True, signed=signed) + if not outname: + outname = self.prefix+"_out" + self.out = Bus(outname, out_N, out_bus=True, signed=signed) self.components = [] self.circuit_wires = [] diff --git a/ariths_gen/multi_bit_circuits/cgp_circuit.py b/ariths_gen/multi_bit_circuits/cgp_circuit.py index 4a9af6c..2334adc 100644 --- a/ariths_gen/multi_bit_circuits/cgp_circuit.py +++ b/ariths_gen/multi_bit_circuits/cgp_circuit.py @@ -41,8 +41,6 @@ class UnsignedCGPCircuit(GeneralCircuit): c_in, c_out, c_rows, c_cols, c_ni, c_no, c_lback = map( int, cgp_prefix.split(",")) - print(cgp_core) - print(cgp_outputs) assert sum( input_widths) == c_in, f"CGP input widht {c_in} doesn't match input_widhts {input_widths}" @@ -106,6 +104,17 @@ class UnsignedCGPCircuit(GeneralCircuit): #print(i, o, w, w.name) self.out.connect(i, w) + @staticmethod + def get_inputs_outputs(code : str): + cgp_prefix, cgp_core, cgp_outputs = re.match( + r"{(.*)}(.*)\(([^()]+)\)", code).groups() + + c_in, c_out, c_rows, c_cols, c_ni, c_no, c_lback = map( + int, cgp_prefix.split(",")) + + return c_in, c_out + + def _get_wire(self, i): if i == 0: return ConstantWireValue0() diff --git a/generate_mac.py b/generate_mac.py index 268f9a3..db17c72 100644 --- a/generate_mac.py +++ b/generate_mac.py @@ -19,7 +19,7 @@ class MAC(GeneralCircuit): # usage if __name__ == "__main__": os.makedirs("test_circuits/mac", exist_ok=True) - mymac = MAC(Bus("a", 8), Bus("b", 8), Bus("acc", 16)) + mymac = MAC(Bus("a", 8), Bus("b", 8), Bus("acc", 16), outname="mac_output") mymac.get_v_code_hier(open("test_circuits/mac/mac_hier.v", "w")) mymac.get_c_code_hier(open("test_circuits/mac/mac_hier.c", "w")) mymac.get_c_code_flat(open("test_circuits/mac/mac_flat.c", "w")) diff --git a/tests/test_circuits_verilog.sh b/tests/test_circuits_verilog.sh index 5302ab2..9617e69 100644 --- a/tests/test_circuits_verilog.sh +++ b/tests/test_circuits_verilog.sh @@ -11,9 +11,6 @@ test_circuit () { for mode in "flat" "hier"; do echo -e "===== Testing verilog \e[33m$circuit\e[0m ($mode) ======" - g++ -std=c++11 -pedantic -g -std=c++11 -pedantic -DCNAME="$circuit" $type.c ../test_circuits/c_circuits/$mode/$circuit.c -o tmp.exe - - if iverilog -o tmp.verilog -Ddut=$circuit ../test_circuits/verilog_circuits/$mode/$circuit.v tb_$type.v ; then tv=`vvp tmp.verilog` if [[ $tv ]]; then