diff --git a/.github/workflows/generate.yml b/.github/workflows/generate.yml
index 52195c6..30d1a76 100644
--- a/.github/workflows/generate.yml
+++ b/.github/workflows/generate.yml
@@ -45,6 +45,8 @@ jobs:
     needs: build
     steps:
     - uses: actions/checkout@v2
+    - name: Install iverilog
+      run: sudo apt install iverilog
     - name: Set up Python 3.x
       uses: actions/setup-python@v2
     - run: python -m pip install numpy
@@ -71,7 +73,11 @@ jobs:
         cd tests
         bash test_mac.sh
         cd ..
-
+    - name: Verilog testing
+      run: |
+        cd tests
+        bash test_circuits_verilog.sh
+        cd ..
 
   test_python:
     runs-on: ubuntu-latest
diff --git a/.gitignore b/.gitignore
index 13f41cf..0cfaf0d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,6 +8,10 @@ dist/
 test_circuits/
 tests/tmp.exe
 tests/tmp.c
+tests/tmp.verilog
 html/
 
-*.egg-info
\ No newline at end of file
+*.egg-info
+
+.pytest_cache
+.ipynb_checkpoints
\ No newline at end of file
diff --git a/tests/tb_adder_signed.v b/tests/tb_adder_signed.v
new file mode 100644
index 0000000..25f7ef7
--- /dev/null
+++ b/tests/tb_adder_signed.v
@@ -0,0 +1,33 @@
+
+`timescale 1 ns/10 ps  // time-unit = 1 ns, precision = 10 ps
+
+module add_signed_tb;
+    reg signed [7:0] a;
+    reg signed [7:0] b;
+    wire signed [8:0] o;
+
+    integer k, j;
+    localparam period = 20;
+
+    `dut dut(a, b, o); //.input_a(a), .input_b(b), .cgp_circuit_out(o));
+
+    always 
+    begin
+
+        for(k = -127; k < 128; k = k+1) begin
+            for(j = -127; j < 128; j = j+1) begin
+
+                assign a = k;
+                assign b = j;
+                
+                #period;
+
+                //$assert(b == 0);c
+                if ( k + j != o) begin
+                    $display("Invalid output: %d + %d = %d", a, b, o);
+                end
+            end;
+        end;
+        $finish;
+    end
+endmodule
\ No newline at end of file
diff --git a/tests/tb_adder_unsigned.v b/tests/tb_adder_unsigned.v
new file mode 100644
index 0000000..2957c41
--- /dev/null
+++ b/tests/tb_adder_unsigned.v
@@ -0,0 +1,33 @@
+
+`timescale 1 ns/10 ps  // time-unit = 1 ns, precision = 10 ps
+
+module add_unsigned_tb;
+    reg [7:0] a;
+    reg [7:0] b;
+    wire [8:0] o;
+
+    integer k, j;
+    localparam period = 20;
+
+    `dut dut(a, b, o); //.input_a(a), .input_b(b), .cgp_circuit_out(o));
+
+    always 
+    begin
+
+        for(k = 0; k < 256; k = k+1) begin
+            for(j = 0; j < 256; j = j+1) begin
+
+                assign a = k;
+                assign b = j;
+                
+                #period;
+
+                //$assert(b == 0);
+                if ( k + j != o) begin
+                    $display("Invalid output: %d + %d = %d", a, b, o);
+                end
+            end;
+        end;
+        $finish;
+    end
+endmodule
\ No newline at end of file
diff --git a/tests/tb_multiplier_signed.v b/tests/tb_multiplier_signed.v
new file mode 100644
index 0000000..67a87bd
--- /dev/null
+++ b/tests/tb_multiplier_signed.v
@@ -0,0 +1,33 @@
+
+`timescale 1 ns/10 ps  // time-unit = 1 ns, precision = 10 ps
+
+module mul_unsigned_tb;
+    reg signed [7:0] a;
+    reg signed [7:0] b;
+    wire signed [15:0] o;
+
+    integer k, j;
+    localparam period = 20;
+
+    `dut dut(a, b, o); //.input_a(a), .input_b(b), .cgp_circuit_out(o));
+
+    always 
+    begin
+
+        for(k = -127; k < 128; k = k+1) begin
+            for(j = -127; j < 128; j = j+1) begin
+
+                assign a = k;
+                assign b = j;
+                
+                #period;
+
+                //$assert(b == 0);
+                if ( k * j != o) begin
+                    $display("Invalid output: %d * %d = %d", a, b, o);
+                end
+            end;
+        end;
+        $finish;
+    end
+endmodule
\ No newline at end of file
diff --git a/tests/tb_multiplier_unsigned.v b/tests/tb_multiplier_unsigned.v
new file mode 100644
index 0000000..4a706ab
--- /dev/null
+++ b/tests/tb_multiplier_unsigned.v
@@ -0,0 +1,33 @@
+
+`timescale 1 ns/10 ps  // time-unit = 1 ns, precision = 10 ps
+
+module mul_unsigned_tb;
+    reg [7:0] a;
+    reg [7:0] b;
+    wire [15:0] o;
+
+    integer k, j;
+    localparam period = 20;
+
+    `dut dut(a, b, o); //.input_a(a), .input_b(b), .cgp_circuit_out(o));
+
+    always 
+    begin
+
+        for(k = 0; k < 256; k = k+1) begin
+            for(j = 0; j < 256; j = j+1) begin
+
+                assign a = k;
+                assign b = j;
+                
+                #period;
+
+                //$assert(b == 0);
+                if ( k * j != o) begin
+                    $display("Invalid output: %d * %d = %d", a, b, o);
+                end
+            end;
+        end;
+        $finish;
+    end
+endmodule
\ No newline at end of file
diff --git a/tests/test_circuits_verilog.sh b/tests/test_circuits_verilog.sh
new file mode 100644
index 0000000..5302ab2
--- /dev/null
+++ b/tests/test_circuits_verilog.sh
@@ -0,0 +1,82 @@
+#!/usr/bin/bash
+
+valid=1
+
+test_circuit () {
+    local type=$1
+    local circuit=$2
+
+
+
+    for mode in "flat" "hier"; do
+        echo -e "===== Testing verilog \e[33m$circuit\e[0m ($mode) ======"
+
+        g++ -std=c++11 -pedantic -g -std=c++11 -pedantic -DCNAME="$circuit" $type.c ../test_circuits/c_circuits/$mode/$circuit.c -o tmp.exe
+
+
+        if iverilog -o tmp.verilog -Ddut=$circuit ../test_circuits/verilog_circuits/$mode/$circuit.v tb_$type.v ; then
+            tv=`vvp tmp.verilog`
+            if [[ $tv ]]; then
+                echo -e "[\e[31mfail\e[0m]"
+                echo -e $tv
+                valid=0
+            else
+                echo -e "[\e[32mok\e[0m]"
+            fi
+        else
+            echo -e "[\e[31mfailed synthesis\e[0m]"
+            valid=0
+        fi
+
+        # if ./tmp.exe ; then
+        #     echo -e "[\e[32mok\e[0m]"
+        # else
+        #     echo -e "[\e[31mfail\e[0m]"
+        #     valid=0
+        # fi
+    done
+}
+
+
+
+test_circuit "adder_signed" "s_rca8"
+test_circuit "adder_signed" "s_pg_rca8"
+test_circuit "adder_signed" "s_cska8"
+test_circuit "adder_signed" "s_cla8"
+
+test_circuit "adder_unsigned" "u_rca8"
+test_circuit "adder_unsigned" "u_pg_rca8"
+test_circuit "adder_unsigned" "u_cska8"
+test_circuit "adder_unsigned" "u_cla8"
+
+
+test_circuit "multiplier_signed" "s_arrmul8" 
+test_circuit "multiplier_signed" "s_wallace_cla8" 
+test_circuit "multiplier_signed" "s_wallace_rca8" 
+test_circuit "multiplier_signed" "s_wallace_pg_rca8" 
+test_circuit "multiplier_signed" "s_wallace_cska8" 
+test_circuit "multiplier_signed" "s_dadda_cla8" 
+test_circuit "multiplier_signed" "s_dadda_rca8" 
+test_circuit "multiplier_signed" "s_dadda_pg_rca8" 
+test_circuit "multiplier_signed" "s_dadda_cska8" 
+
+
+test_circuit "multiplier_unsigned" "u_arrmul8" 
+test_circuit "multiplier_unsigned" "u_wallace_cla8" 
+test_circuit "multiplier_unsigned" "u_wallace_rca8" 
+test_circuit "multiplier_unsigned" "u_wallace_pg_rca8" 
+test_circuit "multiplier_unsigned" "u_wallace_cska8" 
+test_circuit "multiplier_unsigned" "u_dadda_cla8" 
+test_circuit "multiplier_unsigned" "u_dadda_rca8" 
+test_circuit "multiplier_unsigned" "u_dadda_pg_rca8" 
+test_circuit "multiplier_unsigned" "u_dadda_cska8" 
+
+
+
+if [ "$valid" -eq 1 ]; then
+    echo "all tests passed"
+    exit 0
+else 
+    echo "some of tests failed"
+    exit 1
+fi
\ No newline at end of file