diff --git a/ariths_gen/core/cgp_circuit.py b/ariths_gen/core/cgp_circuit.py
index 669fbe0..18daacb 100644
--- a/ariths_gen/core/cgp_circuit.py
+++ b/ariths_gen/core/cgp_circuit.py
@@ -11,10 +11,12 @@ from ariths_gen.one_bit_circuits.logic_gates import (
     NandGate,
     OrGate,
     NorGate,
-    XorGate,
-    XnorGate,
     NotGate
 )
+from ariths_gen.one_bit_circuits.one_bit_components import (
+    XorGateComponent,
+    XnorGateComponent,
+)
 import re
 
 
@@ -98,13 +100,13 @@ class UnsignedCGPCircuit(GeneralCircuit):
             elif fn == 3:  # OR
                 o = self.add_component(OrGate(a, b, **comp_set)).out
             elif fn == 4:  # XOR
-                o = self.add_component(XorGate(a, b, **comp_set)).out
+                o = self.add_component(XorGateComponent(a, b, **comp_set)).out.get_wire(0)
             elif fn == 5:  # NAND
                 o = self.add_component(NandGate(a, b, **comp_set)).out
             elif fn == 6:  # NOR
                 o = self.add_component(NorGate(a, b, **comp_set)).out
             elif fn == 7:  # XNOR
-                o = self.add_component(XnorGate(a, b, **comp_set)).out
+                o = self.add_component(XnorGateComponent(a, b, **comp_set)).out.get_wire(0)
             elif fn == 8:  # TRUE
                 o = ConstantWireValue1()
             elif fn == 9:  # FALSE
diff --git a/ariths_gen/multi_bit_circuits/adders/brent_kung_adder.py b/ariths_gen/multi_bit_circuits/adders/brent_kung_adder.py
index 5415a8e..1bcabca 100644
--- a/ariths_gen/multi_bit_circuits/adders/brent_kung_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/brent_kung_adder.py
@@ -10,9 +10,10 @@ from ariths_gen.one_bit_circuits.one_bit_components import (
     GreyCell,
     BlackCell
 )
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+from ariths_gen.one_bit_circuits.one_bit_components import (
+    XorGateComponent
 )
+
 import math
 
 
@@ -191,6 +192,6 @@ class SignedBrentKungAdder(UnsignedBrentKungAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/carry_increment_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_increment_adder.py
index aa1ad9a..4ec9dfd 100644
--- a/ariths_gen/multi_bit_circuits/adders/carry_increment_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/carry_increment_adder.py
@@ -11,12 +11,12 @@ from ariths_gen.core.logic_gate_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
     FullAdder,
-    FullAdderP
+    FullAdderP,
+    XorGateComponent
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
-    OrGate,
-    XorGate
+    OrGate
 )
 
 
@@ -155,6 +155,6 @@ class SignedCarryIncrementAdder(UnsignedCarryIncrementAdder, GeneralCircuit):
         super().__init__(a=a, b=b, increment_block_size=increment_block_size, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.out.get_wire(-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.out.get_wire(-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py
index e4e82bc..59174d6 100644
--- a/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/carry_lookahead_adder.py
@@ -13,8 +13,10 @@ from ariths_gen.one_bit_circuits.one_bit_components import (
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
-    OrGate,
-    XorGate
+    OrGate
+)
+from ariths_gen.one_bit_circuits.one_bit_components import (
+    XorGateComponent
 )
 
 
@@ -84,8 +86,8 @@ class UnsignedCarryLookaheadAdder(GeneralCircuit):
                 generate_sig.append(pg_block.get_generate_wire())
                 self.add_component(pg_block)
 
-                self.add_component(XorGate(pg_block.get_sum_wire(), cin, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-                self.out.connect(i+(block_n*cla_block_size), self.get_previous_component().out)
+                self.add_component(XorGateComponent(pg_block.get_sum_wire(), cin, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+                self.out.connect(i+(block_n*cla_block_size), self.get_previous_component().out.get_wire(0))
 
                 # List of AND gates outputs that are later combined in a multi-bit OR gate
                 composite_or_gates_inputs = []
@@ -160,8 +162,8 @@ class SignedCarryLookaheadAdder(UnsignedCarryLookaheadAdder, GeneralCircuit):
         super().__init__(a=a, b=b, cla_block_size=cla_block_size, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        sign_xor_1 = XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_1 = XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_1)
-        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(2).out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_2 = XorGateComponent(sign_xor_1.out.get_wire(0), self.get_previous_component(2).out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_2)
-        self.out.connect(self.N, sign_xor_2.out)
+        self.out.connect(self.N, sign_xor_2.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/carry_select_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_select_adder.py
index 6d97ff1..0af25ed 100644
--- a/ariths_gen/multi_bit_circuits/adders/carry_select_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/carry_select_adder.py
@@ -8,12 +8,12 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     FullAdder,
-    TwoOneMultiplexer
+    TwoOneMultiplexer,
+    XorGateComponent
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
-    OrGate,
-    XorGate
+    OrGate
 )
 
 
@@ -164,6 +164,6 @@ class SignedCarrySelectAdder(UnsignedCarrySelectAdder, GeneralCircuit):
         super().__init__(a=a, b=b, select_block_size=select_block_size, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.out.get_wire(-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.out.get_wire(-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py b/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py
index 938d890..e5df682 100644
--- a/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/carry_skip_adder.py
@@ -11,11 +11,11 @@ from ariths_gen.core.logic_gate_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
     FullAdder,
-    TwoOneMultiplexer
+    TwoOneMultiplexer,
+    XorGateComponent
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
-    AndGate,
-    XorGate
+    AndGate
 )
 
 
@@ -80,9 +80,9 @@ class UnsignedCarrySkipAdder(GeneralCircuit):
             block_size = bypass_block_size if N_wires >= bypass_block_size else N_wires
             for i in range(block_size):
                 # Generate propagate wires for corresponding bit pairs
-                propagate_xor = XorGate(a=self.a.get_wire((block_n*bypass_block_size)+i), b=self.b.get_wire((block_n*bypass_block_size)+i), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+                propagate_xor = XorGateComponent(a=self.a.get_wire((block_n*bypass_block_size)+i), b=self.b.get_wire((block_n*bypass_block_size)+i), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
                 self.add_component(propagate_xor)
-                propagate_wires.append(propagate_xor.out)
+                propagate_wires.append(propagate_xor.out.get_wire(0))
 
                 if block_n == 0 and i == 0:
                     obj_adder = HalfAdder(a=self.a.get_wire((block_n*bypass_block_size)+i), b=self.b.get_wire((block_n*bypass_block_size)+i), prefix=self.prefix+"_ha"+str(self.get_instance_num(cls=HalfAdder)))
@@ -159,8 +159,8 @@ class SignedCarrySkipAdder(UnsignedCarrySkipAdder, GeneralCircuit):
         super().__init__(a=a, b=b, bypass_block_size=bypass_block_size, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        sign_xor_1 = XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self)
+        sign_xor_1 = XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self)
         self.add_component(sign_xor_1)
-        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(2).out.get_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self)
+        sign_xor_2 = XorGateComponent(sign_xor_1.out.get_wire(0), self.get_previous_component(2).out.get_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self)
         self.add_component(sign_xor_2)
-        self.out.connect(self.N, sign_xor_2.out)
+        self.out.connect(self.N, sign_xor_2.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/conditional_sum_adder.py b/ariths_gen/multi_bit_circuits/adders/conditional_sum_adder.py
index 5463294..e92f193 100644
--- a/ariths_gen/multi_bit_circuits/adders/conditional_sum_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/conditional_sum_adder.py
@@ -8,10 +8,8 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     FullAdder,
-    TwoOneMultiplexer
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    TwoOneMultiplexer,
+    XorGateComponent
 )
 import math
 
@@ -264,6 +262,6 @@ class SignedConditionalSumAdder(UnsignedConditionalSumAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.out.get_wire(-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.out.get_wire(-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate, count_disabled_gates=False)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/han_carlson_adder.py b/ariths_gen/multi_bit_circuits/adders/han_carlson_adder.py
index 6321418..2f7a2d0 100644
--- a/ariths_gen/multi_bit_circuits/adders/han_carlson_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/han_carlson_adder.py
@@ -8,10 +8,8 @@ from ariths_gen.core.arithmetic_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     PGSumLogic,
     GreyCell,
-    BlackCell
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    BlackCell,
+    XorGateComponent
 )
 import math
 
@@ -221,6 +219,6 @@ class SignedHanCarlsonAdder(UnsignedHanCarlsonAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, config_choice=config_choice, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/knowles_adder.py b/ariths_gen/multi_bit_circuits/adders/knowles_adder.py
index bea9e87..9fd6e9a 100644
--- a/ariths_gen/multi_bit_circuits/adders/knowles_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/knowles_adder.py
@@ -8,10 +8,8 @@ from ariths_gen.core.arithmetic_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     PGSumLogic,
     GreyCell,
-    BlackCell
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    BlackCell,
+    XorGateComponent
 )
 import math
 
@@ -180,6 +178,6 @@ class SignedKnowlesAdder(UnsignedKnowlesAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, config_choice=config_choice, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/kogge_stone_adder.py b/ariths_gen/multi_bit_circuits/adders/kogge_stone_adder.py
index 3aa7d7c..5ae3b77 100644
--- a/ariths_gen/multi_bit_circuits/adders/kogge_stone_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/kogge_stone_adder.py
@@ -8,10 +8,8 @@ from ariths_gen.core.arithmetic_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     PGSumLogic,
     GreyCell,
-    BlackCell
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    BlackCell,
+    XorGateComponent
 )
 import math
 
@@ -164,6 +162,6 @@ class SignedKoggeStoneAdder(UnsignedKoggeStoneAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/ladner_fischer_adder.py b/ariths_gen/multi_bit_circuits/adders/ladner_fischer_adder.py
index a0d170e..a8fa19c 100644
--- a/ariths_gen/multi_bit_circuits/adders/ladner_fischer_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/ladner_fischer_adder.py
@@ -8,10 +8,8 @@ from ariths_gen.core.arithmetic_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     PGSumLogic,
     GreyCell,
-    BlackCell
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    BlackCell,
+    XorGateComponent
 )
 import math
 
@@ -225,6 +223,6 @@ class SignedLadnerFischerAdder(UnsignedLadnerFischerAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, config_choice=config_choice, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py b/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py
index f100019..f1bbd33 100644
--- a/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/pg_ripple_carry_adder.py
@@ -6,12 +6,12 @@ from ariths_gen.core.arithmetic_circuits import (
     GeneralCircuit
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
-    PGSumLogic
+    PGSumLogic,
+    XorGateComponent
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
-    OrGate,
-    XorGate
+    OrGate
 )
 
 
@@ -136,8 +136,8 @@ class SignedPGRippleCarryAdder(UnsignedPGRippleCarryAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        sign_xor_1 = XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_1 = XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_1)
-        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(2).out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_2 = XorGateComponent(sign_xor_1.out.get_wire(0), self.get_previous_component(2).out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_2)
-        self.out.connect(self.N, sign_xor_2.out)
+        self.out.connect(self.N, sign_xor_2.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py b/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py
index a0f4daf..24f43bf 100644
--- a/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py
@@ -6,10 +6,8 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
-    FullAdder
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    FullAdder,
+    XorGateComponent
 )
 
 
@@ -97,8 +95,8 @@ class SignedRippleCarryAdder(UnsignedRippleCarryAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        sign_xor_1 = XorGate(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_1 = XorGateComponent(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_1)
-        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(2).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_2 = XorGateComponent(sign_xor_1.out.get_wire(0), self.get_previous_component(2).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_2)
-        self.out.connect(self.N, sign_xor_2.out)
+        self.out.connect(self.N, sign_xor_2.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/adders/sklansky_adder.py b/ariths_gen/multi_bit_circuits/adders/sklansky_adder.py
index 1785627..8643541 100644
--- a/ariths_gen/multi_bit_circuits/adders/sklansky_adder.py
+++ b/ariths_gen/multi_bit_circuits/adders/sklansky_adder.py
@@ -8,10 +8,8 @@ from ariths_gen.core.arithmetic_circuits import (
 from ariths_gen.one_bit_circuits.one_bit_components import (
     PGSumLogic,
     GreyCell,
-    BlackCell
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    BlackCell,
+    XorGateComponent
 )
 
 
@@ -167,6 +165,6 @@ class SignedSklanskyAdder(UnsignedSklanskyAdder, GeneralCircuit):
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        self.add_component(XorGate(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.add_component(XorGate(self.get_previous_component().out, self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self))
-        self.out.connect(self.N, self.get_previous_component().out)
+        self.add_component(XorGateComponent(self.a.get_wire(self.N-1), self.b.get_wire(self.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.add_component(XorGateComponent(self.get_previous_component().out.get_wire(0), self.get_previous_component(2).get_generate_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self))
+        self.out.connect(self.N, self.get_previous_component().out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_carry_save_multiplier.py b/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_carry_save_multiplier.py
index 2f9e94d..4739b7e 100644
--- a/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_carry_save_multiplier.py
+++ b/ariths_gen/multi_bit_circuits/approximate_multipliers/broken_carry_save_multiplier.py
@@ -9,6 +9,9 @@ from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
     FullAdder
 )
+from ariths_gen.core.logic_gate_circuits import (
+    ThreeInputLogicGate
+)
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate
 )
@@ -184,7 +187,7 @@ class UnsignedBrokenCarrySaveMultiplier(MultiplierCircuit):
                     previous_sums.append(ConstantWireValue0())
                 else:
                     prev_sum_obj = self.get_previous_component((final_cpa_N-2-wire_id)*2) if wire_id < final_cpa_N-2 else self.get_previous_component()
-                    if isinstance(prev_sum_obj, TwoInputLogicGate):
+                    if isinstance(prev_sum_obj, ThreeInputLogicGate):
                         previous_sums.append(prev_sum_obj.out)
                     else:
                         previous_sums.append(prev_sum_obj.get_sum_wire())
@@ -192,7 +195,7 @@ class UnsignedBrokenCarrySaveMultiplier(MultiplierCircuit):
                     previous_carries.append(ConstantWireValue0())
                 else:
                     prev_carry_obj = self.get_previous_component((final_cpa_N-2-wire_id)*2+2)
-                    if isinstance(prev_carry_obj, TwoInputLogicGate):
+                    if isinstance(prev_carry_obj, ThreeInputLogicGate):
                         previous_carries.append(prev_carry_obj.out)
                     else:
                         previous_carries.append(prev_carry_obj.get_carry_wire())
diff --git a/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py b/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py
index 9795bdc..3cf24ad 100644
--- a/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py
+++ b/ariths_gen/multi_bit_circuits/approximate_multipliers/recursive_multiplier.py
@@ -8,12 +8,14 @@ from ariths_gen.core.arithmetic_circuits import (
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
     OrGate,
-    XorGate,
     NotGate
 )
 from ariths_gen.multi_bit_circuits.adders import (
     UnsignedCarryLookaheadAdder
 )
+from ariths_gen.one_bit_circuits.one_bit_components import (
+    XorGateComponent
+)
 import math
 
 
@@ -64,15 +66,15 @@ class UnsignedAccurateTwoBitMultiplier(MultiplierCircuit):
         and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and2")
         and_obj4 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and3")
 
-        xor_obj1 = XorGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
+        xor_obj1 = XorGateComponent(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
         and_obj5 = AndGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_and4")
-        xor_obj2 = XorGate(and_obj5.out, and_obj4.out, prefix=self.prefix+"_xor1")
+        xor_obj2 = XorGateComponent(and_obj5.out, and_obj4.out, prefix=self.prefix+"_xor1")
         and_obj6 = AndGate(and_obj5.out, and_obj4.out, prefix=self.prefix+"_and5")
         [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, xor_obj1, and_obj5, xor_obj2, and_obj6]]
 
         self.out.connect(0, and_obj1.out)
-        self.out.connect(1, xor_obj1.out)
-        self.out.connect(2, xor_obj2.out)
+        self.out.connect(1, xor_obj1.out.get_wire(0))
+        self.out.connect(2, xor_obj2.out.get_wire(0))
         self.out.connect(3, and_obj6.out)
 
 
@@ -209,14 +211,14 @@ class UnsignedApproximateTwoBitMultiplierM2(MultiplierCircuit):
         and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and2")
 
         and_obj4 = AndGate(and_obj1.out, and_obj2.out, prefix=self.prefix+"_and3")
-        xor_obj1 = XorGate(and_obj1.out, and_obj2.out, prefix=self.prefix+"_xor0")
+        xor_obj1 = XorGateComponent(and_obj1.out, and_obj2.out, prefix=self.prefix+"_xor0")
 
-        xor_obj2 = XorGate(and_obj4.out, and_obj3.out, prefix=self.prefix+"_xor1")
+        xor_obj2 = XorGateComponent(and_obj4.out, and_obj3.out, prefix=self.prefix+"_xor1")
         [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, xor_obj1, xor_obj2]]
 
         self.out.connect(0, and_obj4.out)
-        self.out.connect(1, xor_obj1.out)
-        self.out.connect(2, xor_obj2.out)
+        self.out.connect(1, xor_obj1.out.get_wire(0))
+        self.out.connect(2, xor_obj2.out.get_wire(0))
         self.out.connect(3, and_obj4.out)
 
 
@@ -360,11 +362,11 @@ class UnsignedApproximateTwoBitMultiplierM4(MultiplierCircuit):
         and_obj3 = AndGate(self.a.get_wire(1), self.b.get_wire(0), prefix=self.prefix+"_and2")
         and_obj4 = AndGate(self.a.get_wire(1), self.b.get_wire(1), prefix=self.prefix+"_and3")
 
-        xor_obj1 = XorGate(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
+        xor_obj1 = XorGateComponent(and_obj2.out, and_obj3.out, prefix=self.prefix+"_xor0")
         [self.add_component(obj) for obj in [and_obj1, and_obj2, and_obj3, and_obj4, xor_obj1]]
 
         self.out.connect(0, and_obj1.out)
-        self.out.connect(1, xor_obj1.out)
+        self.out.connect(1, xor_obj1.out.get_wire(0))
         self.out.connect(2, and_obj4.out)
         self.out.connect(3, ConstantWireValue0())
 
diff --git a/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py
index 3979f17..0961282 100644
--- a/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py
+++ b/ariths_gen/multi_bit_circuits/multipliers/array_multiplier.py
@@ -8,13 +8,13 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
-    FullAdder
+    FullAdder,
+    XorGateComponent
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
     AndGate,
     NandGate,
-    NorGate,
-    XorGate
+    NorGate
 )
 
 
@@ -235,7 +235,7 @@ class SignedArrayMultiplier(MultiplierCircuit):
                     self.out.connect(b_multiplier_index + a_multiplicand_index, obj_adder.get_sum_wire())
 
                     if a_multiplicand_index == self.N-1:
-                        obj_xor = XorGate(self.get_previous_component().get_carry_wire(), ConstantWireValue1(), prefix=self.prefix+"_xor"+str(a_multiplicand_index+1)+"_"+str(b_multiplier_index), parent_component=self)
+                        obj_xor = XorGateComponent(self.get_previous_component().get_carry_wire(), ConstantWireValue1(), prefix=self.prefix+"_xor"+str(a_multiplicand_index+1)+"_"+str(b_multiplier_index), parent_component=self)
                         self.add_component(obj_xor)
 
-                        self.out.connect(self.out.N-1, obj_xor.out)
+                        self.out.connect(self.out.N-1, obj_xor.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py
index c6f9971..5b2c1d2 100644
--- a/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py
+++ b/ariths_gen/multi_bit_circuits/multipliers/dadda_multiplier.py
@@ -11,10 +11,8 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
-    FullAdder
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    FullAdder,
+    XorGateComponent
 )
 
 
@@ -231,6 +229,6 @@ class SignedDaddaMultiplier(MultiplierCircuit):
             [self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
 
         # Final XOR to ensure proper sign extension
-        obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        obj_xor = XorGateComponent(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(obj_xor)
-        self.out.connect(self.out.N-1, obj_xor.out)
+        self.out.connect(self.out.N-1, obj_xor.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py b/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py
index 6cf165a..0a0c946 100644
--- a/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py
+++ b/ariths_gen/multi_bit_circuits/multipliers/wallace_multiplier.py
@@ -11,10 +11,8 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
-    FullAdder
-)
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
+    FullAdder,
+    XorGateComponent
 )
 from ariths_gen.multi_bit_circuits.adders import (
     CarrySaveAdderComponent,
@@ -314,9 +312,9 @@ class SignedWallaceMultiplier(MultiplierCircuit):
                 [self.out.connect(o, final_adder.out.get_wire(o), inserted_wire_desired_index=o) for o in range(0, final_adder.out.N-1)]
 
             # Final XOR to ensure proper sign extension
-            obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+            obj_xor = XorGateComponent(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
             self.add_component(obj_xor)
-            self.out.connect(self.out.N-1, obj_xor.out)
+            self.out.connect(self.out.N-1, obj_xor.out.get_wire(0))
 
         # FULLY INTERCONNECTED HAs/FAs IMPLEMENTATION
         else:
@@ -394,6 +392,6 @@ class SignedWallaceMultiplier(MultiplierCircuit):
                 [self.out.connect(o, final_adder.out.get_wire(o-1), inserted_wire_desired_index=o-1) for o in range(1, len(self.out.bus))]
 
             # Final XOR to ensure proper sign extension
-            obj_xor = XorGate(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+            obj_xor = XorGateComponent(ConstantWireValue1(), self.out.get_wire(self.out.N-1), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
             self.add_component(obj_xor)
-            self.out.connect(self.out.N-1, obj_xor.out)
+            self.out.connect(self.out.N-1, obj_xor.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/others/bit_reduce.py b/ariths_gen/multi_bit_circuits/others/bit_reduce.py
index 2cabd83..3ef0397 100644
--- a/ariths_gen/multi_bit_circuits/others/bit_reduce.py
+++ b/ariths_gen/multi_bit_circuits/others/bit_reduce.py
@@ -9,7 +9,7 @@ from ariths_gen.one_bit_circuits.logic_gates import (
     OrGate
 )
 from ariths_gen.core.logic_gate_circuits import (
-    TwoInputLogicGate
+    ThreeInputLogicGate
 )
 
 
@@ -17,7 +17,7 @@ class BitReduce(GeneralCircuit):
     """Class representing tree reducer circuit. Doent work for NAND gate!
     """
 
-    def __init__(self, a: Bus, gate: TwoInputLogicGate, prefix: str = "", name: str = "bitreduce", **kwargs):
+    def __init__(self, a: Bus, gate: ThreeInputLogicGate, prefix: str = "", name: str = "bitreduce", **kwargs):
         self.N = a.N
         super().__init__(name=name, prefix=prefix, inputs=[a], out_N=1, **kwargs)
 
diff --git a/ariths_gen/multi_bit_circuits/others/compare.py b/ariths_gen/multi_bit_circuits/others/compare.py
index 205ba5a..b0e2fc6 100644
--- a/ariths_gen/multi_bit_circuits/others/compare.py
+++ b/ariths_gen/multi_bit_circuits/others/compare.py
@@ -42,7 +42,7 @@ class UnsignedCompareLT(GeneralCircuit):
             and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
             res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
 
-            pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
+            pi = self.add_component(XnorGateComponent(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out.get_wire(0)
             psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
 
 
@@ -75,7 +75,7 @@ class UnsignedCompareLTE(GeneralCircuit):
             and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
             res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
 
-            pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
+            pi = self.add_component(XnorGateComponent(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out.get_wire(0)
             psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
 
         res[self.N] = psum # or all equal (xor)
@@ -112,7 +112,7 @@ class UnsignedCompareGT(GeneralCircuit):
             and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}")).out
             res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}")).out
 
-            pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
+            pi = self.add_component(XnorGateComponent(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out.get_wire(0)
             psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}")).out
 
 
@@ -145,7 +145,7 @@ class UnsignedCompareGTE(GeneralCircuit):
             and1 = self.add_component(AndGate(i1, i2, f"{self.prefix}_and1_{i}", parent_component=self)).out
             res[i] = self.add_component(AndGate(and1, psum, f"{self.prefix}_and2_{i}", parent_component=self)).out
 
-            pi = self.add_component(XnorGate(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out
+            pi = self.add_component(XnorGateComponent(iA, iB, f"{self.prefix}_pi_{i}", parent_component=self)).out.get_wire(0)
             psum = self.add_component(AndGate(pi, psum, f"{self.prefix}_psum_{i}", parent_component=self)).out
 
         res[self.N] = psum # or all equal (xor)
diff --git a/ariths_gen/multi_bit_circuits/subtractors/ripple_borrow_subtractor.py b/ariths_gen/multi_bit_circuits/subtractors/ripple_borrow_subtractor.py
index cd6ffd0..31a5e44 100644
--- a/ariths_gen/multi_bit_circuits/subtractors/ripple_borrow_subtractor.py
+++ b/ariths_gen/multi_bit_circuits/subtractors/ripple_borrow_subtractor.py
@@ -6,12 +6,9 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfSubtractor,
-    FullSubtractor
+    FullSubtractor,
+    XorGateComponent
 )
-from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate
-)
-
 
 class UnsignedRippleBorrowSubtractor(GeneralCircuit):
     """Class representing unsigned ripple borrow subtractor.
@@ -94,8 +91,8 @@ class SignedRippleBorrowSubtractor(UnsignedRippleBorrowSubtractor, GeneralCircui
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
         
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        sign_xor_1 = XorGate(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_1 = XorGateComponent(self.get_previous_component(1).a, self.get_previous_component(1).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_1)
-        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(2).get_borrow_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_2 = XorGateComponent(sign_xor_1.out.get_wire(0), self.get_previous_component(2).get_borrow_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_2)
-        self.out.connect(self.N, sign_xor_2.out)
+        self.out.connect(self.N, sign_xor_2.out.get_wire(0))
diff --git a/ariths_gen/multi_bit_circuits/subtractors/ripple_carry_subtractor.py b/ariths_gen/multi_bit_circuits/subtractors/ripple_carry_subtractor.py
index 9d783c5..c67ad74 100644
--- a/ariths_gen/multi_bit_circuits/subtractors/ripple_carry_subtractor.py
+++ b/ariths_gen/multi_bit_circuits/subtractors/ripple_carry_subtractor.py
@@ -6,10 +6,11 @@ from ariths_gen.core.arithmetic_circuits import (
 )
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
-    FullAdder
+    FullAdder,
+    XorGateComponent
 )
 from ariths_gen.one_bit_circuits.logic_gates import (
-    XorGate, NotGate
+    NotGate
 )
 from ariths_gen.wire_components.wires import ConstantWireValue1
 
@@ -101,8 +102,8 @@ class SignedRippleCarrySubtractor(UnsignedRippleCarrySubtractor, GeneralCircuit)
         super().__init__(a=a, b=b, prefix=prefix, name=name, signed=True, **kwargs)
 
         # Additional XOR gates to ensure correct sign extension in case of sign addition
-        sign_xor_1 = XorGate(self.get_previous_component(2).a, self.get_previous_component(2).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_1 = XorGateComponent(self.get_previous_component(2).a, self.get_previous_component(2).b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_1)
-        sign_xor_2 = XorGate(sign_xor_1.out, self.get_previous_component(3).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        sign_xor_2 = XorGateComponent(sign_xor_1.out.get_wire(0), self.get_previous_component(3).get_carry_wire(), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(sign_xor_2)
-        self.out.connect(self.N, sign_xor_2.out)
+        self.out.connect(self.N, sign_xor_2.out.get_wire(0))
diff --git a/ariths_gen/one_bit_circuits/logic_gates/__init__.py b/ariths_gen/one_bit_circuits/logic_gates/__init__.py
index de1174a..5002015 100644
--- a/ariths_gen/one_bit_circuits/logic_gates/__init__.py
+++ b/ariths_gen/one_bit_circuits/logic_gates/__init__.py
@@ -3,7 +3,5 @@ from .logic_gates import (
     NandGate,
     OrGate,
     NorGate,
-    XorGate,
-    XnorGate,
     NotGate
 )
diff --git a/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py b/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
index b3d3ce6..a7934de 100644
--- a/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
+++ b/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
@@ -97,67 +97,6 @@ class NorGate(Maji):
     def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
         super().__init__(a, b, ConstantWireValue0(), prefix=prefix, inverts=[True, True, False], outid=outid, parent_component=parent_component)
 
-class XorGate(Maji):
-    """Class representing two input XOR gate.
-
-    ```
-        ┌──────┐
-    ───►│ =1   │
-        │      ├─►
-    ───►│      │
-        └──────┘
-    ```
-
-    Description of the __init__ method.
-
-    Args:
-        a (Wire): First input wire.
-        b (Wire): Second input wire.
-        prefix (str, optional): Prefix name of XOR gate. Defaults to "".
-        outid (int, optional): Index of output wire. Defaults to 0.
-        parent_component (object, optional) Object of upper component of which XOR gate is a subcomponent. Defaults to None.
-    """
-    def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
-
-        super().__init__(a, b, ConstantWireValue0(), prefix=prefix, inverts=[True, True, False], outid=outid, parent_component=parent_component)
-        """super().__init__(a, b, prefix=prefix, outid=outid, parent_component=parent_component)
-
-        self.and1  = Maji(a, b, ConstantWireValue0(), prefix=prefix, inverts=[True,  False, False], parent_component = parent_component)
-        self.and2  = Maji(a, b, ConstantWireValue0(), prefix=prefix, inverts=[False, True,  False], parent_component = parent_component)
-        self.orOut = Maji(self.and1.out, self.and2.out, ConstantWireValue1(), prefix=prefix, parent_component = parent_component)
-        self.out  = self.orOut.out"""
-
-
-class XnorGate(Maji):
-    """Class representing two input XNOR gate.
-
-    ```
-        ┌──────┐
-    ───►│ =1   │
-        │      │O──►
-    ───►│      │
-        └──────┘
-    ```
-
-    Description of the __init__ method.
-
-    Args:
-        a (Wire): First input wire.
-        b (Wire): Second input wire.
-        prefix (str, optional): Prefix name of XNOR gate. Defaults to "".
-        outid (int, optional): Index of output wire. Defaults to 0.
-        parent_component (object, optional) Object of upper component of which XNOR gate is a subcomponent. Defaults to None.
-    """
-    def __init__(self, a: Wire, b: Wire, prefix: str = "", outid:  int = 0, parent_component: object = None):
-        """super().__init__(a, b, prefix=prefix, outid=outid, parent_component=parent_component)
-
-        self.and1  = Maji(a, b, ConstantWireValue0(), prefix=prefix, inverts=[True,  False, False], parent_component = parent_component)
-        self.and2  = Maji(a, b, ConstantWireValue0(), prefix=prefix, inverts=[False, True,  False], parent_component = parent_component)
-        self.orOut = Maji(self.and1.out, self.and2.out, ConstantWireValue1(), prefix=prefix, parent_component = parent_component)
-        self.out  = self.orOut.out"""
-        super().__init__(a, b, ConstantWireValue0(), prefix=prefix, inverts=[True, True, False], outid=outid, parent_component=parent_component)
-
-
 # Single-input #
 class NotGate(Maji):
     """Class representing one input NOT gate.
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/__init__.py b/ariths_gen/one_bit_circuits/one_bit_components/__init__.py
index b1a946a..2300838 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/__init__.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/__init__.py
@@ -8,6 +8,8 @@ from .three_input_one_bit_components import (
     FullAdder,
     FullAdderP,
     FullAdderPG,
+    XorGateComponent,
+    XnorGateComponent,
     PGSumLogic,
     TwoOneMultiplexer,
     FullSubtractor,
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/four_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/four_input_one_bit_components.py
index cc51287..1ba2903 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/four_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/four_input_one_bit_components.py
@@ -1,6 +1,7 @@
 from ariths_gen.wire_components.wires import ConstantWireValue0
 from ariths_gen.core.one_bit_circuits import FourInputOneBitCircuit
-from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, XorGate, XnorGate, NotGate
+from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
+from ariths_gen.one_bit_circuits.one_bit_components import XorGateComponent, XnorGateComponent
 from ariths_gen.wire_components import Wire, Bus
 
 
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
index 438fcbf..4481fca 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
@@ -1,7 +1,8 @@
 from ariths_gen.one_bit_circuits import Maji
 from ariths_gen.wire_components.wires import ConstantWireValue0
 from ariths_gen.core.one_bit_circuits import ThreeInputOneBitCircuit
-from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, XorGate, XnorGate, NotGate
+from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
+from .two_input_one_bit_components import XorGateComponent, XnorGateComponent
 from ariths_gen.wire_components import Wire, Bus
 
 
@@ -211,18 +212,18 @@ class PGSumLogic(ThreeInputOneBitCircuit):
         self.out = Bus(self.prefix+"_out", 3)
 
         # PG logic
-        propagate_xor = XorGate(a, b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), outid=0, parent_component=self)
+        propagate_xor = XorGateComponent(a, b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=0, parent_component=self)
         self.add_component(propagate_xor)
-        self.out.connect(0, propagate_xor.out)
+        self.out.connect(0, propagate_xor.out.get_wire(0))
 
         generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
         self.add_component(generate_and)
         self.out.connect(1, generate_and.out)
 
         # Sum output
-        sum_xor = XorGate(propagate_xor.out, c, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), outid=2, parent_component=self)
+        sum_xor = XorGateComponent(propagate_xor.out.get_wire(0), c, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=2, parent_component=self)
         self.add_component(sum_xor)
-        self.out.connect(2, sum_xor.out)
+        self.out.connect(2, sum_xor.out.get_wire(0))
 
     def get_propagate_wire(self):
         """Get output wire carrying propagate signal value.
@@ -289,11 +290,11 @@ class TwoOneMultiplexer(ThreeInputOneBitCircuit):
         and_obj = AndGate(a=self.a, b=self.get_previous_component().out, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), parent_component=self)
         self.add_component(and_obj)
 
-        xor_obj = XorGate(a=self.get_previous_component(3).out, b=self.get_previous_component().out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        xor_obj = XorGateComponent(a=self.get_previous_component(3).out, b=self.get_previous_component().out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(xor_obj)
 
         # Connection of MUX output wire
-        self.out.connect(0, xor_obj.out)
+        self.out.connect(0, xor_obj.out.get_wire(0))
 
     def get_mux_out_wire(self):
         """Get multiplexer output wire.
@@ -377,7 +378,7 @@ class FullSubtractor(ThreeInputOneBitCircuit):
         self.out = Bus(self.prefix+"_out", 2)
 
         # Difference
-        xor_obj = XorGate(a=self.a, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), parent_component=self)
+        xor_obj = XorGateComponent(a=self.a, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), parent_component=self)
         self.add_component(xor_obj)
 
         not_obj = NotGate(a=self.a, prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
@@ -386,12 +387,12 @@ class FullSubtractor(ThreeInputOneBitCircuit):
         and_obj = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), parent_component=self)
         self.add_component(and_obj)
 
-        difference_xor = XorGate(a=self.c, b=xor_obj.out, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), outid=0, parent_component=self)
+        difference_xor = XorGateComponent(a=self.c, b=xor_obj.out.get_wire(0), prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=0, parent_component=self)
         self.add_component(difference_xor)
-        self.out.connect(0, difference_xor.out)
+        self.out.connect(0, difference_xor.out.get_wire(0))
 
         # Borrow out
-        not_obj = NotGate(a=xor_obj.out, prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
+        not_obj = NotGate(a=xor_obj.out.get_wire(0), prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
         self.add_component(not_obj)
 
         and_obj = AndGate(a=not_obj.out, b=self.c, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), parent_component=self)
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
index 6f38e77..2489198 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
@@ -1,8 +1,81 @@
 from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit
-from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, XorGate, XnorGate, NotGate
+from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
 from ariths_gen.one_bit_circuits import Maji
 from ariths_gen.wire_components import Wire, Bus
-from ariths_gen.wire_components.wires import ConstantWireValue0
+from ariths_gen.wire_components.wires import ConstantWireValue0, ConstantWireValue1
+
+
+class XorGateComponent(TwoInputOneBitCircuit):
+    """Class representing two input XOR gate.
+
+    ```
+        ┌──────┐
+    ───►│ =1   │
+        │      ├─►
+    ───►│      │
+        └──────┘
+    ```
+
+    Description of the __init__ method.
+
+    Args:
+        a (Wire): First input wire.
+        b (Wire): Second input wire.
+        prefix (str, optional): Prefix name of XOR gate. Defaults to "".
+        outid (int, optional): Index of output wire. Defaults to 0.
+        parent_component (object, optional) Object of upper component of which XOR gate is a subcomponent. Defaults to None.
+    """
+    def __init__(self, a: Wire, b: Wire, prefix: str = "", outid: int = 0, parent_component: object = None):
+        super().__init__(a, b, prefix=prefix, name=prefix)
+        
+        self.out = Bus(self.prefix+"_out", 1)
+
+        obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False],  prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
+        self.add_component(obj_and1)
+        
+        obj_and2 = Maji(a, b, ConstantWireValue1(), inverts=[False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
+        self.add_component(obj_and2)
+
+        # sum
+        obj_and3 = Maji(obj_and1.out, obj_and2.out, ConstantWireValue0(), [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=outid, parent_component=parent_component)
+        self.add_component(obj_and3)
+        self.out.connect(0, obj_and3.out)
+
+class XnorGateComponent(TwoInputOneBitCircuit):
+    """Class representing two input XNOR gate.
+
+    ```
+        ┌──────┐
+    ───►│ =1   │
+        │      │O──►
+    ───►│      │
+        └──────┘
+    ```
+
+    Description of the __init__ method.
+
+    Args:
+        a (Wire): First input wire.
+        b (Wire): Second input wire.
+        prefix (str, optional): Prefix name of XNOR gate. Defaults to "".
+        outid (int, optional): Index of output wire. Defaults to 0.
+        parent_component (object, optional) Object of upper component of which XNOR gate is a subcomponent. Defaults to None.
+    """
+    def __init__(self, a: Wire, b: Wire, prefix: str = "", outid:  int = 0, parent_component: object = None):
+        super().__init__(a, b, prefix=prefix, name=prefix)
+        
+        self.out = Bus(self.prefix+"_out", 1)
+
+        obj_and1 = Maji(a, b, ConstantWireValue1(), inverts=[True, True, False],  prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
+        self.add_component(obj_and1)
+        
+        obj_and2 = Maji(a, b, ConstantWireValue1(), inverts=[False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), parent_component = parent_component)
+        self.add_component(obj_and2)
+
+        # sum
+        obj_and3 = Maji(obj_and1.out, obj_and2.out, ConstantWireValue1(), [True, True, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=outid, parent_component=parent_component)
+        self.add_component(obj_and3)
+        self.out.connect(0, obj_and3.out)
 
 
 class HalfAdder(TwoInputOneBitCircuit):
@@ -131,12 +204,12 @@ class PGLogicBlock(TwoInputOneBitCircuit):
         self.add_component(propagate_or)
         generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
         self.add_component(generate_and)
-        sum_xor = XorGate(a, b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), outid=2, parent_component=self)
+        sum_xor = XorGateComponent(a, b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=2, parent_component=self)
         self.add_component(sum_xor)
 
         self.out.connect(0, propagate_or.out)
         self.out.connect(1, generate_and.out)
-        self.out.connect(2, sum_xor.out)
+        self.out.connect(2, sum_xor.out.get_wire(0))
 
     def get_propagate_wire(self):
         """Get output wire carrying propagate signal value.
@@ -189,16 +262,16 @@ class HalfSubtractor(TwoInputOneBitCircuit):
 
         # Difference
         # XOR gate for calculation of 1-bit difference
-        difference_xor = XorGate(a=self.a, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), outid=0, parent_component=self)
+        difference_xor = XorGateComponent(a=self.a, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=0, parent_component=self)
         self.add_component(difference_xor)
-        self.out.connect(0, difference_xor.out)
+        self.out.connect(0, difference_xor.out.get_wire(0))
 
         # Bout
         # NOT and AND gates for calculation of 1-bit borrow out
         not_obj = NotGate(a=self.a, prefix=self.prefix+"_not"+str(self.get_instance_num(cls=NotGate)), parent_component=self)
         self.add_component(not_obj)
 
-        borrow_and = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGate)), outid=1, parent_component=self)
+        borrow_and = AndGate(a=not_obj.out, b=self.b, prefix=self.prefix+"_xor"+str(self.get_instance_num(cls=XorGateComponent)), outid=1, parent_component=self)
         self.add_component(borrow_and)
         self.out.connect(1, borrow_and.out)
 
diff --git a/generate_test.py b/generate_test.py
index 4426239..f040f9f 100644
--- a/generate_test.py
+++ b/generate_test.py
@@ -10,14 +10,14 @@ from ariths_gen.one_bit_circuits.logic_gates import (
     NandGate,
     OrGate,
     NorGate,
-    XorGate,
-    XnorGate,
     NotGate
 )
 
 from ariths_gen.one_bit_circuits.one_bit_components import (
     HalfAdder,
     FullAdder,
+    XorGateComponent,
+    XnorGateComponent,
     PGLogicBlock,
     FullAdderPG,
     TwoOneMultiplexer,
diff --git a/tests/test_all.py b/tests/test_all.py
index 11ce60e..4385d56 100644
--- a/tests/test_all.py
+++ b/tests/test_all.py
@@ -74,11 +74,14 @@ from ariths_gen.one_bit_circuits.logic_gates import (
     NandGate,
     OrGate,
     NorGate,
-    XorGate,
-    XnorGate,
     NotGate
 )
 
+from ariths_gen.one_bit_circuits.one_bit_components import (
+    XorGateComponent,
+    XnorGateComponent
+)
+
 
 def test_unsigned_approxmul(values=False):
     """ Test unsigned approximate multipliers """
diff --git a/tests/test_maji_adder.py b/tests/test_maji_adder.py
index 5c62b80..e8b2e63 100644
--- a/tests/test_maji_adder.py
+++ b/tests/test_maji_adder.py
@@ -34,7 +34,7 @@ if __name__ == "__main__":
             expectedBus = (a + b) & 0xFF
 
         if (expectedBus != testOut):
-            print(f"expexted {expectedBus} have {testOut}")
+            print(f"expexted {a} + {b} = {expectedBus} have {testOut}")
             exit(1)
         
     print("Test maji as Ripple Carry Adder OK")
diff --git a/tests/test_maji_gates.py b/tests/test_maji_gates.py
index d2b01b6..2db0adc 100644
--- a/tests/test_maji_gates.py
+++ b/tests/test_maji_gates.py
@@ -6,6 +6,7 @@ sys.path.insert(0, os.path.join(DIR_PATH, '..'))
 
 from ariths_gen.core.arithmetic_circuits import GeneralCircuit
 from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, NorGate, NotGate, OrGate
+from ariths_gen.one_bit_circuits.one_bit_components import XorGateComponent, XnorGateComponent
 from ariths_gen.wire_components import Bus
 
 from ariths_gen.pdk import *
@@ -15,22 +16,26 @@ class MultiMaji(GeneralCircuit):
     def __init__(self, a: Bus, b: Bus, prefix: str = "", name: str = "maji", **kwargs):
         super().__init__(prefix=prefix, name=name, out_N=a.N, inputs=[a, b], **kwargs)
 
-        self.out = Bus("out", a.N * 5)
+        self.out = Bus("out", a.N * 7)
 
         assert a.N == b.N
 
         for i in range(a.N):
-            self.orGate   = self.add_component(  OrGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="or"))
-            self.andGate  = self.add_component( AndGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="and"))
-            self.norGate  = self.add_component( NorGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="nor"))
-            self.nandGate = self.add_component(NandGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="nand"))
-            self.notGate  = self.add_component( NotGate(a.get_wire(i), parent_component=self, prefix="not"))
+            self.orGate    = self.add_component(  OrGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="or"))
+            self.andGate   = self.add_component( AndGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="and"))
+            self.norGate   = self.add_component( NorGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="nor"))
+            self.nandGate  = self.add_component(NandGate(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="nand"))
+            self.notGate   = self.add_component( NotGate(a.get_wire(i), parent_component=self, prefix="not"))
+            self.xorGate   = self.add_component( XorGateComponent(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="xor"))
+            self.xnorGate  = self.add_component( XnorGateComponent(a.get_wire(i), b.get_wire(i), parent_component=self, prefix="xnor"))
 
             self.out.connect(i          , self.orGate.out)
             self.out.connect(a.N     + i, self.andGate.out)
             self.out.connect(a.N * 2 + i, self.norGate.out)
             self.out.connect(a.N * 3 + i, self.nandGate.out)
             self.out.connect(a.N * 4 + i, self.notGate.out)
+            self.out.connect(a.N * 5 + i, self.xorGate.out.get_wire())
+            self.out.connect(a.N * 6 + i, self.xnorGate.out.get_wire())
 
 # usage
 if __name__ == "__main__":
@@ -43,7 +48,7 @@ if __name__ == "__main__":
 
         testOut = maji(a, b)
 
-        expectedBus = (a | b) | (a & b) << 1 | (~(a | b) & 0b1) << 2 | (~(a & b) & 0b1) << 3 | (~a & 0b1) << 4
+        expectedBus = (a | b) | (a & b) << 1 | (~(a | b) & 0b1) << 2 | (~(a & b) & 0b1) << 3 | (~a & 0b1) << 4 | (a ^ b) << 5 | (~(a ^ b) & 0b1) << 6
 
         if (expectedBus != testOut):
             print(f"expexted {expectedBus} have {testOut}")